MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture

2019 ◽  
Author(s):  
Joonseop Sim ◽  
Minsu Kim ◽  
Yeseong Kim ◽  
Saransh Gupta ◽  
Behnam Khaleghi ◽  
...  
Keyword(s):  
High Performance ◽  
Memory Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

2021 ◽  
Vol 11 (3) ◽  
pp. 29
Author(s):  
Tommaso Zanotti ◽  
Francesco Maria Puglisi ◽  
Paolo Pavan
Keyword(s):  
Neural Networks ◽  
High Performance ◽  
Random Access ◽  
Resistive Random Access Memory ◽  
Hardware Accelerators ◽  
Memory Architecture ◽  
Ultra Low Power ◽  
Von Neumann ◽  
Non Volatile Memory ◽  
Volatile Memory

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.

Octopus + : An RDMA-Enabled Distributed Persistent Memory File System

2021 ◽  
Vol 17 (3) ◽  
pp. 1-25
Author(s):  
Bohong Zhu ◽  
Youmin Chen ◽  
Qing Wang ◽  
Youyou Lu ◽  
Jiwu Shu
Keyword(s):  
High Speed ◽  
High Performance ◽  
File System ◽  
Direct Memory Access ◽  
File Systems ◽  
Distributed File Systems ◽  
Persistent Memory ◽  
Memory Modules ◽  
Non Volatile Memory ◽  
Volatile Memory

Non-volatile memory and remote direct memory access (RDMA) provide extremely high performance in storage and network hardware. However, existing distributed file systems strictly isolate file system and network layers, and the heavy layered software designs leave high-speed hardware under-exploited. In this article, we propose an RDMA-enabled distributed persistent memory file system, Octopus + , to redesign file system internal mechanisms by closely coupling non-volatile memory and RDMA features. For data operations, Octopus + directly accesses a shared persistent memory pool to reduce memory copying overhead, and actively fetches and pushes data all in clients to rebalance the load between the server and network. For metadata operations, Octopus + introduces self-identified remote procedure calls for immediate notification between file systems and networking, and an efficient distributed transaction mechanism for consistency. Octopus + is enabled with replication feature to provide better availability. Evaluations on Intel Optane DC Persistent Memory Modules show that Octopus + achieves nearly the raw bandwidth for large I/Os and orders of magnitude better performance than existing distributed file systems.

scholarly journals Efektivitas alat tes servis bolavoli berbasis mikrokontroller

2020 ◽  
Vol 6 (2) ◽  
pp. 499-513
Author(s):  
Giartama Giartama ◽  
Destriani Destriani ◽  
Waluyo Waluyo ◽  
Muslimin Muslimin
Keyword(s):  
Low Power ◽  
High Performance ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Microcontroller Unit

Ilmu pengetahuan dengan cepat harus menyesuaikan dengan tuntutan zaman. Berbagai cabang olahraga telah menggunakan kemajuan teknologi sebagai penunjang kegiatan baik dalam pembelajaran ataupun saat latihan khususnya pada olahraga cabang permainan bolavoli. Penelitian ini bertujuan untuk menguji efektivitas alat tes servis bolavoli berbasis mikrokontroller yang terdiri dari komponen-komponen seperti high performance, low power avr® 8-bit microcontroller unit, advanced risc architecture, high endurance non-volatile memory segments, peripheral features, special microcontroller features, dan menggunakan perangkat yang lain agar dapat digunakan untuk mengukur tes servis bolavoli. Penelitian ini menggunakan metode penelitian kuantitatif. Instrumen tes yang digunakan berupa tes keterampilan servis bolavoli. Subjek dalam penelitian ini yaitu untuk kelas pemula subjek penelitian mahasiswa semester 2 yang bukan merupakan atlet bolavoli, kemudian pada mahasiswa yang ekstrakurikulernya bolavoli, dan kelompok ketiga pada mahasiswa yang termasuk pada atlet nasional dan daerah dengan jumlah subjek sebanyak 60 orang. Hasil dari penelitian ini didapatkan nilai keefektifan sebesar 99,04% dengan mengklasifikasikan subjek penelitian menjadi tiga tingkat yang berbeda. Berdasarkan hasil tersebut dapat disimpulkan bahwa alat tes servis bolavoli berbasis mikrokontroller ini efektif digunakan baik bagi pemula hingga atlet professional.

NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture

2018 ◽  
Vol 74 (8) ◽  
pp. 3875-3903
Author(s):  
Danqi Hu ◽  
Fang Lv ◽  
Chenxi Wang ◽  
Hui-Min Cui ◽  
Lei Wang ◽  
...  
Keyword(s):  
Memory Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory

2014 ◽  
Vol 22 (2) ◽  
pp. 125-139 ◽  
Author(s):  
Myoungsoo Jung ◽  
Ellis H. Wilson ◽  
Wonil Choi ◽  
John Shalf ◽  
Hasan Metin Aktulga ◽  
...  
Keyword(s):  
High Performance ◽  
File Systems ◽  
Network Capacity ◽  
General Purpose ◽  
Graphical Processing Units ◽  
Non Volatile Memory ◽  
Order Of Magnitude ◽  
Volatile Memory ◽  
Graphical Processing ◽  
Point To Point

Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.

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