Parallel Computing of Graph-based Functions in ReRAM

Resistive Random Access Memory (ReRAM) is an emerging non-volatile memory technology. Besides its low power consumption and its high scalability, its inherent computation capabilities make ReRAM especially interesting for future computer architectures. Merging computations into the memory is a promising solution for overcoming the memory bottleneck. To perform computations in ReRAM, efficient synthesis strategies for Boolean functions have to be developed. In this article, we give a thorough presentation of how to employ parallel computing capabilities of ReRAM for the synthesis of functions given state-of-the-art graph-based representations AIGs or BDDs. Additionally, we introduce a new graph-based representation called m-And-Inverter Graph (m-AIGs), which allows us to fully exploit the computing capabilities of ReRAM. In the simulations, we show that our proposed approaches outperform state-of-the art synthesis strategies, and we show the superiority of m-AIGs over the standard AIG representation for ReRAM-based synthesis.

A Spiking Neuromorphic Architecture Using Gated-RRAM for Associative Memory

This work reports a spiking neuromorphic architecture for associative memory simulated in a SPICE environment using recently reported gated-RRAM (resistive random-access memory) devices as synapses alongside neurons based on complementary metal-oxide semiconductors (CMOSs). The network utilizes a Verilog A model to capture the behavior of the gated-RRAM devices within the architecture. The model uses parameters obtained from experimental gated-RRAM devices that were fabricated and tested in this work. Using these devices in tandem with CMOS neuron circuitry, our results indicate that the proposed architecture can learn an association in real time and retrieve the learned association when incomplete information is provided. These results show the promise for gated-RRAM devices for associative memory tasks within a spiking neuromorphic architecture framework.

Sol-Gel Processed ZrO2 Based Forming-Free Resistive Switching Memory Devices

In this work, we fabricated ZrO2 based resistive random access memory by sol-gel spin coating technique and investigated its structural, optical and resistive switching properties. The X-ray diffraction pattern revealed that 400 °C annealed ZrO2 thin film has tetragonal structure. The optical band gap value of ZrO2 thin film obtained was 5.51 eV. The resistive switching behaviour of W/ZrO2/ITO capacitor like structure was studied. It was found that no initial electroforming process required for the device. The fabricated devices show a self-compliance bipolar resistive switching behaviour and have high on off ratio (>102). Our result suggests that solution processed ZrO2 has great potential to develop transparent and flexible resistive random access memory devices.

Modeling of Gate Tunable Synaptic Device for Neuromorphic Applications

The emerging memories are great candidates to establish neuromorphic computing challenging non-Von Neumann architecture. Emerging non-volatile resistive random-access memory (RRAM) attracted abundant attention recently for its low power consumption and high storage density. Up to now, research regarding the tunability of the On/Off ratio and the switching window of RRAM devices remains scarce. In this work, the underlying mechanisms related to gate tunable RRAMs are investigated. The principle of such a device consists of controlling the filament evolution in the resistive layer using graphene and an electric field. A physics-based stochastic simulation was employed to reveal the mechanisms that link the filament size and the growth speed to the back-gate bias. The simulations demonstrate the influence of the negative gate voltage on the device current which in turn leads to better characteristics for neuromorphic computing applications. Moreover, a high accuracy (94.7%) neural network for handwritten character digit classification has been realized using the 1-transistor 1-memristor (1T1R) crossbar cell structure and our stochastic simulation method, which demonstrate the optimization of gate tunable synaptic device.

Adaptation Strategies for Personalized Gait Neuroprosthetics

Personalization of gait neuroprosthetics is paramount to ensure their efficacy for users, who experience severe limitations in mobility without an assistive device. Our goal is to develop assistive devices that collaborate with and are tailored to their users, while allowing them to use as much of their existing capabilities as possible. Currently, personalization of devices is challenging, and technological advances are required to achieve this goal. Therefore, this paper presents an overview of challenges and research directions regarding an interface with the peripheral nervous system, an interface with the central nervous system, and the requirements of interface computing architectures. The interface should be modular and adaptable, such that it can provide assistance where it is needed. Novel data processing technology should be developed to allow for real-time processing while accounting for signal variations in the human. Personalized biomechanical models and simulation techniques should be developed to predict assisted walking motions and interactions between the user and the device. Furthermore, the advantages of interfacing with both the brain and the spinal cord or the periphery should be further explored. Technological advances of interface computing architecture should focus on learning on the chip to achieve further personalization. Furthermore, energy consumption should be low to allow for longer use of the neuroprosthesis. In-memory processing combined with resistive random access memory is a promising technology for both. This paper discusses the aforementioned aspects to highlight new directions for future research in gait neuroprosthetics.

A Novel RFID Authentication Protocol Based on Reconfigurable RRAM PUF

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries. Aiming at the current light-weight RFID encryption scheme with limited information protection methods, combined with the physical unclonable function (PUF) composed of resistive random access memory (RRAM), a new type of high-efficiency reconfigurable strong PUF circuit structure is proposed in this paper. Experimental results show that the proposed PUF shows an almost ideal value (50%) of inter-chip hamming distance (HD) (µ/σ = 0.5001/0.0340) among 1000 PUF keys, and intra-chip HD results are very close to the ideal value (0). The bit error rate (BER) is as low as 3.8×10−6 across one million challenges. Based on the RRAM PUF, we propose and implement a light weight RFID authentication protocol. By virtue of RRAM’s model ability, the protocol replaces the One-way Hash Function with a response chain mutual encryption algorithm. The results of test and analysis show that the protocol can effectively resist multiple threats such as physical attacks, replay attacks, tracking attacks and asynchronous attacks, and has good stability. At the same time, based on RRAM’s unique resistance variability, PUF also has the advantage of being reconfigurable, providing good security for RFID tags.