Technology mapping is the final step of logic synthesis which consists of mapping an optimized technology
independent logic network representation into a circuit realization in a given technology. An important component
of the technology mapping problem is the identification of feasible library cells for the realization of the logic
operators in the logic tree. There are two main classes of such matching algorithms. Library-based matching
algorithms [1–4] require that all available physical components be represented explicitly in a pattern library.
Sections of the logic network are then matched against this pattern list for the identification of suitable
components. In contrast, cell generator-based matching techniques [6–8] accept feasibility constraints on the
complexity and quantity of physical components according to limits imposed by the target technology or the
capabilities of the cell generator. Hence, individual patterns are not stored in a library and are instead generated
as needed. In this paper, we present a new cell generator-based constructive matching algorithm. Because the
algorithm builds matched patterns incrementally, very large cell families can be accommodated using time and
space resources that are proportional to the size of the largest feasible cell pattern and not the size of the library
of patterns as would be the case for library-based approaches. Also, whereas existing cell generator-based
matching techniques combine the tasks of matching (identification) and covering (selection), constructive matching
provides more flexibility by not restricting the covering phase. Empirical results demonstrate the increased quality
of the technology-mapped circuits when larger cells are available.
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
