Development of the yield enhancement system of a high-volume 8-inch wafer fab

Author(s):  
Ping Wang ◽  
M. Chan ◽  
R. Goodner ◽  
F. Lee ◽  
R. Ceton
2019 ◽  
Author(s):  
Chien Ming Wu ◽  
Chin Kuei Chang ◽  
Yousheng Yin ◽  
Jeffery Liang ◽  
Chia Ping Chen ◽  
...  
Keyword(s):  

Author(s):  
Ryan Ross ◽  
Gil Garteiz

Abstract Driving yield improvement activities to decrease baseline logic / scan yield fallout is often perceived as a challenging or complex activity. Much of this perception is based on yield or device teams historical interactions with the FA teams on these types of requests. This paper will present our methodology for generating a relatively high volume of scan FA results in a short time frame. This type of high volume scan FA enables real time FA paretos of what is causing scan / logic yield loss.


2009 ◽  
Author(s):  
Katsushi Nakano ◽  
Rei Seki ◽  
Toshiyuki Sekito ◽  
Masato Yoshida ◽  
Tomoharu Fujiwara ◽  
...  

2010 ◽  
Author(s):  
Katsushi Nakano ◽  
Rei Seki ◽  
Tadamasa Kawakubo ◽  
Yoshihiro Maruta ◽  
Toshiyuki Sekito ◽  
...  

2012 ◽  
Vol 25 (1) ◽  
pp. 63-71 ◽  
Author(s):  
Hamid R. Khorram ◽  
Katsushi Nakano ◽  
Natsuko Sagawa ◽  
Tomoharu Fujiwara ◽  
Yasuhiro Iriuchijima ◽  
...  

2012 ◽  
Author(s):  
Natsuko Sagawa ◽  
Katsushi Nakano ◽  
Yuuki Ishii ◽  
Kazunori Kusabiraki ◽  
Motoyuki Shima

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