An ultra low power digitally controlled oscillator with low jitter and high resolution

2010 ◽  
Author(s):  
Nasser Erfani Majd ◽  
Mojtaba Lotfizad ◽  
Arash Abadian ◽  
Mohammad Bagher Ghaznavi Ghoushchi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Ultra Low Power ◽  
Digitally Controlled ◽  
Low Jitter ◽  
Digitally Controlled Oscillator

scholarly journals An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

2011 ◽  
Vol 8 (21) ◽  
pp. 1801-1807 ◽  
Author(s):  
Arash Abadian ◽  
Mojtaba Lotfizad ◽  
M.B. Ghaznavi-Ghoushchi ◽  
Nasser Erfani Majd
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Low Complexity ◽  
Ultra Low Power ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

scholarly journals An ultra low-power digitally controlled oscillator using novel Schmitt-trigger based hysteresis delay cells

2011 ◽  
Vol 8 (8) ◽  
pp. 589-595 ◽  
Author(s):  
Nasser Erfani Majd ◽  
Mojtaba Lotfizad ◽  
M.B Ghaznavi-Ghoushchi ◽  
Arash Abadian
Keyword(s):  
Low Power ◽  
Schmitt Trigger ◽  
Ultra Low Power ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

scholarly journals A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1336
Author(s):  
Zixuan Wang ◽  
Hongyang Wu ◽  
Xin Wang ◽  
Mingmin Shi ◽  
Shanwen Hu ◽  
...  
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Multi Stage ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
The Cost ◽  
Lc Tank

This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply.

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