scholarly journals An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

2011 ◽  
Vol 8 (21) ◽  
pp. 1801-1807 ◽  
Author(s):  
Arash Abadian ◽  
Mojtaba Lotfizad ◽  
M.B. Ghaznavi-Ghoushchi ◽  
Nasser Erfani Majd
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Low Complexity ◽  
Ultra Low Power ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

scholarly journals An ultra low-power digitally controlled oscillator using novel Schmitt-trigger based hysteresis delay cells

2011 ◽  
Vol 8 (8) ◽  
pp. 589-595 ◽  
Author(s):  
Nasser Erfani Majd ◽  
Mojtaba Lotfizad ◽  
M.B Ghaznavi-Ghoushchi ◽  
Arash Abadian
Keyword(s):  
Low Power ◽  
Schmitt Trigger ◽  
Ultra Low Power ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

scholarly journals A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1336
Author(s):  
Zixuan Wang ◽  
Hongyang Wu ◽  
Xin Wang ◽  
Mingmin Shi ◽  
Shanwen Hu ◽  
...  
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Multi Stage ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
The Cost ◽  
Lc Tank

This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply.

scholarly journals A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

2019 ◽  
Vol 17 ◽  
pp. 145-150
Author(s):  
Markus Scholl ◽  
Ralf Wunderlich ◽  
Stefan Heinen
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Calibration Method ◽  
Low Complexity ◽  
Frequency Stability ◽  
Wireless Communication Systems ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Digital Frequency ◽  
Frequency Calibration

Abstract. This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems. This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its send- and receive-state to achieve frequency stability over process variation and temperature drifts. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power oscillator's by utilizing non-linear segmented feedback levels. In measurements the proposed calibration method improves the frequency stability of an ultra-low-power 32 kHz oscillator from 53 to 10 ppm ∘C−1 over a wide temperature range for temperature drifts of less than 1 ∘C s−1 with an estimated power consumption of 185 nW while coping with relocking periods of 7 ms.

An Ultra-Low Power Holter and Low Complexity Design Using Mixed Signal Processor

2013 ◽  
Vol 284-287 ◽  
pp. 1627-1632
Author(s):  
Hsieh Chang Huang ◽  
Ching Tang Hsieh ◽  
Guang Lin Hsieh
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Ecg Signal ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sd Card ◽  
Signal Processor

An ultra-low power, portable, and easily implemented Holter recorder is necessary for patients or researchers of electrocardiogram (ECG). Such a Holter recorder with off-the-shelf components is realized with mixed signal processor (MSP) in this paper. To decrease the complexity of analog circuits and the interference of 60 Hz noise from power line, we use the MSP to implement a finite impulse response (FIR) filter which is equiripple design. We also integrate the ring buffer for the input samples and the symmetrical characteristic of the FIR filter for efficiently computing convolution. The experimental results show that the ECG output signal with the PQRST feature is easy to be distinguished. This ECG signal is recorded for 24 hours using a SD card. Furthermore, the ECG signal is transmitted with a smartphone via Bluetooth to decrease the burden of the Holter recorder. As a result, this paper uses the Lomb method for the spectral analysis of Heart Rate Variability (HRV) better than Fast Fourier Transform (FFT).

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