Successive Approximation Register (SAR) analog to digital Converters (ADC) is favorable choice for the high resolution. As resolution of ADC increases, the no. of redundant cycles increases which increases power. So the Paper presents clock gated ADC with no redundant cycles/transition cycles for low power requirement and comparison between without Clock Gating and Clock Gated SAR. Using Simulation, Power consumption for Clock gated SAR 736.1nW at 1.8V power supply where as without Clock Gating SAR consumption is 54µW at 1.8 power supply.
Design of an ultra-low power SA-ADC with medium/high resolution and speed