Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier

2005 ◽  
Vol 40 (3) ◽  
pp. 726-735 ◽  
Author(s):  
Kwangseok Han ◽  
J. Gil ◽  
Seong-Sik Song ◽  
Jeonghu Han ◽  
Hyungcheol Shin ◽  
...  
Keyword(s):  
High Frequency ◽  
Thermal Noise ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Short Channel ◽  
Noise Modeling ◽  
Noise Amplifier

A wideband BiCMOS thermal noise canceling low noise amplifier with temperature compensation

2015 ◽  
Vol 57 (9) ◽  
pp. 2121-2125
Author(s):  
Zheng Hao Lu ◽  
Xiao Peng Yu ◽  
Kiat Seng Yeo ◽  
Wei Meng Lim
Keyword(s):  
Temperature Compensation ◽  
Thermal Noise ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier ◽  
Noise Canceling

scholarly journals A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8476
Author(s):  
Yuxuan Tang ◽  
Yulang Feng ◽  
He Hu ◽  
Cheng Fang ◽  
Hao Deng ◽  
...  
Keyword(s):  
High Frequency ◽  
Harmonic Distortion ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Ultrasound Transducers ◽  
High Frequency Ultrasound ◽  
Front End ◽  
Noise Amplifier ◽  
Frequency Ultrasound

This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers. The LNA employs a resistive shunt-feedback structure with a feedforward noise-canceling technique to accomplish both wideband impedance matching and low noise performance. A complementary CMOS topology was also developed to cancel out the second-order harmonic distortion and enhance the amplifier linearity. A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), was designed and fabricated in a 180 nm CMOS process. At 80 MHz, the front-end achieves an input-referred noise density of 1.36 nV/sqrt (Hz), an input return loss (S11) of better than −16 dB, a voltage gain of 37 dB, and a total harmonic distortion (THD) of −55 dBc while dissipating a power of 37 mW, leading to a noise efficiency factor (NEF) of 2.66.

STUDY OF PARASITIC CAPACITANCE EFFECT ON NOISE FIGURE OF IDCLNA IN DEEP SUBMICRON CMOS TECHNOLOGIES

2014 ◽  
Vol 23 (05) ◽  
pp. 1450058
Author(s):  
S. MANJULA ◽  
D. SELVATHI
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Current Gain ◽  
Cmos Process ◽  
Short Channel ◽  
Trade Offs ◽  
Noise Amplifier ◽  
The Impact

Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f T ) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.

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