scholarly journals A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving <-44-dBc HD3 Up To 1.5-V ${_{{p-p}}}$ Output Swing Over 0.01-5.4-GHz for Direct RF Sampling Applications

2021 ◽  
pp. 1-1
Author(s):  
Anoop Narayan Bhat ◽  
Ronan A. R. van der Zee ◽  
Bram Nauta
Keyword(s):  
Low Noise ◽  
Active Balun ◽  
Output Swing ◽  
Rf Sampling

scholarly journals Active Balun with Center-Tapped Inductor and Double-Balanced Gilbert Mixer for GNSS Applications

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1351
Author(s):  
Daniel Pietron ◽  
Tomasz Borejko ◽  
Witold Adam Pleskacz
Keyword(s):  
Phase Shift ◽  
Noise Figure ◽  
Low Noise ◽  
Global Navigation Satellite Systems ◽  
Cmos Process ◽  
Differential Signal ◽  
Satellite Systems ◽  
Active Balun ◽  
Noise Amplifier ◽  
Global Navigation Satellite

A new 1.575 GHz active balun with a classic double-balanced Gilbert mixer for global navigation satellite systems is proposed herein. A simple, low-noise amplifier architecture is used with a center-tapped inductor to generate a differential signal equal in amplitude and shifted in phase by 180°. The main advantage of the proposed circuit is that the phase shift between the outputs is always equal to 180°, with an accuracy of ±5°, and the gain difference between the balun outputs does not change by more than 1.5 dB. This phase shift and gain difference between the outputs are also preserved for all process corners, as well as temperature and voltage supply variations. In the balun design, a band calibration system based on a switchable capacitor bank is proposed. The balun and mixer were designed with a 110 nm CMOS process, consuming only a 2.24 mA current from a 1.5 V supply. The measured noise figure and conversion gain of the balun and mixer were, respectively, NF = 7.7 dB and GC = 25.8 dB in the band of interest.

An Energy-Efficient Receiver for Human Body Communication

2012 ◽  
Vol 195-196 ◽  
pp. 84-89
Author(s):  
Da Hui Zhang ◽  
Ze Dong Nie ◽  
Feng Guan ◽  
Lei Wang
Keyword(s):  
Low Power ◽  
Human Body ◽  
Data Transmission ◽  
Energy Efficient ◽  
Low Noise ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Variable Gain ◽  
Active Balun ◽  
Noise Amplifier

A low-power, wideband signaling receiver for data transmission through a human body was presented in this paper. The receiver utilized a novel implementation of energy-efficient wideband impulse communication that uses the human body as the transmission medium, provides low power consumption, high reception sensitivity. The receiver consists of a low-noise amplifier, active balun, variable gain amplifier (VGA) Gm-C filter, comparator, and FSK demodulator. It was designed with 0.18um CMOS process in an active area of 1.54mm0.414mm. Post-simulation showed that the receiver has a gain range of-2dB~40dB. The receiver consumes 4mW at 1.8V supply and achieves transmission bit energy of 0.8nJ/bit.

A 20-GHz low-noise amplifier with active balun in a 0.25-/spl mu/m SiGe BICMOS technology

2005 ◽  
Vol 40 (10) ◽  
pp. 2092-2097 ◽  
Author(s):  
B. Welch ◽  
K.T. Kornegay ◽  
Hyun-Min Park ◽  
J. Laskar
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Active Balun ◽  
Noise Amplifier

A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture

2018 ◽  
Vol 28 (02) ◽  
pp. 1950022
Author(s):  
Arumugam Sathishkumar ◽  
Siddhan Saravanan
Keyword(s):  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Noise ◽  
Clock Frequency ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Capacitance ◽  
Simulation Results ◽  
Output Swing

A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

1.8 dB NF 3.6 mW CMOS active balun low noise amplifier for GPS

2010 ◽  
Vol 46 (3) ◽  
pp. 239 ◽  
Author(s):  
Y. Ji ◽  
C. Wang ◽  
J. Liu ◽  
H. Liao
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Active Balun ◽  
Noise Amplifier
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