Density-of-State and Trap Modeling of Low-Voltage Electric-Double-Layer TFTs

2011 ◽  
Vol 32 (4) ◽  
pp. 512-514 ◽  
Author(s):  
Mingzhi Dai ◽  
Jie Jiang ◽  
Yue Yang ◽  
Guodong Wu ◽  
Qing Wan
RSC Advances ◽  
2020 ◽  
Vol 10 (14) ◽  
pp. 8093-8096
Author(s):  
Wei Dou ◽  
Yuanyuan Tan

Dual gate (DG) low-voltage transparent electric-double-layer (EDL) thin-film transistors (TFTs) with microporous-SiO2 for both top and bottom dielectrics have been fabricated, both dielectrics were deposited by plasma-enhanced chemical vapor deposition (PECVD).


2014 ◽  
Vol 35 (4) ◽  
pp. 482-484 ◽  
Author(s):  
Ning Liu ◽  
Yanghui Liu ◽  
Liqiang Zhu ◽  
Yi Shi ◽  
Qing Wan

2011 ◽  
Vol 32 (11) ◽  
pp. 1543-1545 ◽  
Author(s):  
Wei Dou ◽  
Jie Jiang ◽  
Jia Sun ◽  
Bin Zhou ◽  
Qing Wan

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