Three dimensional dielectrophoretic assembly of singlewalled carbon nanotubes for integrated circuit interconnects

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

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Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2015p0154 ◽

2015 ◽

Author(s):

Halit Dogan ◽

Md Mahbub Alam ◽

Navid Asadizanjani ◽

Sina Shahbazmohamadi ◽

Domenic Forte ◽

...

Keyword(s):

Integrated Circuits ◽

Integrated Circuit ◽

3D Imaging ◽

Three Dimensional ◽

Serial Sectioning ◽

Promising Technique ◽

Flash Memories ◽

X Ray ◽

3D Information ◽

The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

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Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

The Open Electrical & Electronic Engineering Journal ◽

10.2174/1874129001509010170 ◽

2015 ◽

Vol 9 (1) ◽

pp. 170-174 ◽

Cited By ~ 3

Author(s):

Xiaoling Zhang ◽

Qingduan Meng ◽

Liwen Zhang

Keyword(s):

Thermal Shock ◽

Indium Antimonide ◽

Integrated Circuit ◽

Focal Plane ◽

Three Dimensional ◽

Fracture Probability ◽

Focal Plane Arrays ◽

Thermal Shock Test ◽

Readout Integrated Circuit ◽

Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

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