Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

2008 ◽  
Author(s):  
Nicholas Randall ◽  
Rahul Premachandran Nair
Keyword(s):  
Mechanical Properties ◽  
Quality Control ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Solder Bumps ◽  
Initial Work ◽  
Circuit Components ◽  
Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Circuit Tracing on Integrated Circuit Using FIB Passive Voltage Contrast Effect

2015 ◽  
Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer ◽  
Michael W. Phaneuf
Keyword(s):  
Electron Microscope ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Database System ◽  
Conventional Procedure ◽  
Sem Imaging ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Graphic Database

Abstract Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

In SEM a New Method of Internal Micrographic Visualization of Semiconductor Materials and IC by Crossing the Surface

2001 ◽  
Vol 7 (S2) ◽  
pp. 484-485
Author(s):  
Ling Xiao ◽  
Zhuguan Liang ◽  
Yawen Li ◽  
Jian Wang ◽  
Kailin Zhou ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Silicon Oxide ◽  
Detection Method ◽  
New Method ◽  
Semiconductor Materials ◽  
Contactless Method ◽  
Quality And Reliability ◽  
Nitride Layers ◽  
Scanning Electron

In the paper, we firstly publish a new method of internal micrographic visualization of semiconductor and IC. The quality and reliability of the semiconductor materials (SM) and the integrated circuits (IC) have always been concerned Having a high resolution, high reliable and nondestructive detection method is the key element for their improvements.Silicon oxide layers are used to provide the electrical insulation in the multi-structured ICs. The IC device surfaces are often protected by silicon oxide and silicon nitride layers. Therefore, these insulation layers also cover any inhomogeneity and defect located within the IC devices. It is necessary to have an examining method to detect those defects that are under the insulation layers without damaging the samples. However, the conventional scanning electron microscope (SEM) cannot be utilized to image and examine the surfaces that are positioned below the insulation layers.Novel nondestructive and contactless method has been developed in our laboratory to obtain the internal micrograph that crosses the surface of the semiconductor material and the integrated circuit.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

2003 ◽  
Author(s):  
Ashok Raman ◽  
Marek Turowski ◽  
Monte Mar
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Ic ◽  
Localized Heating ◽  
3D Integrated Circuits ◽  
Thermal Simulations

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

scholarly journals Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions

Materials ◽  
2019 ◽  
Vol 12 (22) ◽  
pp. 3713 ◽  
Author(s):  
Fei Zhao
Keyword(s):  
Electron Microscope ◽  
Integrated Circuit ◽  
Seed Layer ◽  
High Reliability ◽  
Through Silicon Vias ◽  
X Ray ◽  
Layer Structures ◽  
Silicon Vias ◽  
Scanning Electron

The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.

Subsurface Imaging of Multi-Level Integrated Circuits Using Scanning Electron Acoustic Microscopy

2009 ◽  
Author(s):  
L. Meng ◽  
J.C.H. Phang ◽  
A.G. Street
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Modulation Frequency ◽  
Acoustic Microscopy ◽  
Subsurface Imaging ◽  
Phase Images ◽  
Different Depths ◽  
Multi Level ◽  
Electron Acoustic ◽  
Scanning Electron

Abstract The capability of the Scanning Electron Acoustic Microscopy (SEAM) technique for high resolution non-destructive subsurface imaging at different depths for a multi-level integrated circuit is assessed. Experimental results using a beveled DRAM IC sample are used to quantify the effect of the electron beam energy and modulation frequency on contrast, spatial resolution and depth of focus of SEAM amplitude and phase images.

Failure Analysis of FinFET Circuitry at GHz Speeds Using Voltage-Contrast and Stroboscopic Techniques on a Scanning Electron Microscope

2019 ◽  
Author(s):  
James Vickers ◽  
Seema Somani ◽  
Blake Freeman ◽  
Pete Carleson ◽  
Lubomír Tùma ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Electrical Activity ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Contrast Mechanism ◽  
Voltage Contrast ◽  
Working Device ◽  
Scanning Electron

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Effect of Intermetallic Compounds on the Thermomechanical Fatigue Life of Three-Dimensional Integrated Circuit Package Microsolder Bumps: Finite Element Analysis and Study

2015 ◽  
Vol 137 (4) ◽  
Author(s):  
Soud Farhan Choudhury ◽  
Leila Ladani
Keyword(s):  
Fatigue Life ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Volume Fraction ◽  
Three Dimensional ◽  
Strain Range ◽  
Bulk Solder ◽  
Element Analysis ◽  
Plastic Strain Range ◽  
Inelastic Strains

Currently, intermetallics (IMCs) in the solder joint are getting much attention due to their higher volume fraction in the smaller thickness interconnects. They possess different mechanical properties compared to bulk solder. Large volume fraction of IMCs may affect the mechanical behavior, thermomechanical and mechanical fatigue life and reliability of the solder interconnects due to very brittle nature compared to solder material. The question that this study is seeking to answer is how degrading IMCs are to the thermomechanical reliability of the microbumps used in three-dimensional (3D) integrated circuits (ICs) where the microsolder bumps have only a few microns of bond thicknesses. Several factors such as “squeezed out” solder geometry and IMC thickness are studied through a numerical experiment. Fatigue life is calculated using Coffin–Manson model. Results show that, though undesirable because of high likelihood of creating short circuits, squeezed out solder accumulates less inelastic strains under thermomechanical cyclic load and has higher fatigue life. The results show that with the increase of IMCs thickness in each model, the inelastic strains accumulation per cycle increases, thus decreasing the fatigue life. The drop in fatigue life tends to follow an exponential decay path. On the other hand, it was observed that plastic strain range per cycle tends to develop rapidly in Cu region with the increase in IMC thickness which calls for a consideration of Cu fatigue life more closely when the microbump contains a higher volume fraction of the IMCs. Overall, by analyzing the results, it is obvious that the presence of IMCs must be considered for microsolder bump with smaller bond thickness in fatigue life prediction model to generate more reasonable and correct results.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

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