Modeling and simulation of wideband low jitter frequency synthesizer

Author(s):  
A.A. Telba
2019 ◽  
Vol 54 (12) ◽  
pp. 3466-3477 ◽  
Author(s):  
Juyeop Kim ◽  
Younghyun Lim ◽  
Heein Yoon ◽  
Yongsun Lee ◽  
Hangi Park ◽  
...  

2013 ◽  
Vol 284-287 ◽  
pp. 2627-2631
Author(s):  
Hsin Chuan Chen

In many applications such as digital communication systems, a reconfigurable clock is required to switch the desired frequency at necessary time. However, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems, therefore phase-interpolation approaches are used to generate a pulse or clock with correct time intervals. Focusing on design methodology, a high-precision DDS-like clock generator without phase accumulator and phase interpolation is proposed in this paper, which only uses the bidirectional integration on a single capacitor to directly achieve the clock output with correct time intervals. It also can avoid the impact on frequency error caused by the capacitance error. Therefore, the proposed DDS-like clock generator using bidirectional integration can provides a low-jitter and high-precision clock output, and it also has less hardware complexity.


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