This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.
In this paper the fractional order integrative operator s−m, where m is a real positive number, is approximated via a mathematical formula and then an hardware implementation of fractional integral operator is proposed using Field Programmable Gate Array (FPGA). Digital hardware implementation of fractional-order integral operator requires careful consideration of issue of system performance, hardware cost, and hardware speed. FPGA-based implementation are up to one hundred times faster than implementations based on micro-processors; this extra speed can be exploited to allow higher performance in terms of digital approximations of fractional-order systems.
An Extremely Simple Multi-Wing Chaotic System: Dynamics Analysis, Encryption Application and Hardware Implementation
