In this paper the fractional order integrative operator s−m, where m is a real positive number, is approximated via a mathematical formula and then an hardware implementation of fractional integral operator is proposed using Field Programmable Gate Array (FPGA). Digital hardware implementation of fractional-order integral operator requires careful consideration of issue of system performance, hardware cost, and hardware speed. FPGA-based implementation are up to one hundred times faster than implementations based on micro-processors; this extra speed can be exploited to allow higher performance in terms of digital approximations of fractional-order systems.
