Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

scholarly journals A SIMULATION MODEL FOR ROBOT’S SLIP DISPLACEMENT SENSORS

2016 ◽  
pp. 224-236 ◽  
Author(s):  
Yuriy Kondratenko ◽  
Oleksandr Gerasin ◽  
Andriy Topalov
Keyword(s):  
Simulation Model ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Displacement Sensor ◽  
Clamping Force ◽  
Sensing System ◽  
Displacement Sensors ◽  
Field Programmable ◽  
Slip Displacement ◽  
Corrosive Environments

This paper deals with a simulation model of slip displacement sensors for the object slip signals’ registration in the adaptive robot’s gripper. The study presents the analysis of different methods for slip displacement signals detection, as well as authors’ solutions. Special attention is paid to the investigations of the developed sensor with the resistive registration element in rod type structure of sensitive elements, which is able to operate in harsh and corrosive environments. A sensing system for the object slip signals’ registration in the adaptive robot’s gripper with a clamping force correction is developed for proposed slip displacement sensor with multi-component resistive registration elements. The hardware implementation of the sensing system for slip signals’ registration and obtained results are considered in details. The simulation model of the proposed slip displacement sensor based on polytypic conductive rubber is modeled by Proteus software. The intelligent approaches with the use of a field programmable gate array (FPGA) and VHDL-model to the sensing system designing allow to define the slippage direction in slip displacement sensor based on resistive registration elements. Thus, this expands the functionality of the developed sensor.

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

scholarly journals A Luenberger-Like Observer for Multistable Kapitaniak Chaotic System

Complexity ◽  
2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
J. Humberto Pérez-Cruz ◽  
Jacobo Marcos Allende Peña ◽  
Christian Nwachioma ◽  
Jose de Jesus Rubio ◽  
Jaime Pacheco ◽  
...  
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Estimation Error ◽  
Lipschitz Constant ◽  
Experimental Results ◽  
Good Agreement

The objective of this paper is to estimate the unmeasurable variables of a multistable chaotic system using a Luenberger-like observer. First, the observability of the chaotic system is analyzed. Next, a Lipschitz constant is determined on the attractor of this system. Then, the methodology proposed by Raghavan and the result proposed by Thau are used to try to find an observer. Both attempts are unsuccessful. In spite of this, a Luenberger-like observer can still be used based on a proposed gain. The performance of this observer is tested by numerical simulation showing the convergence to zero of the estimation error. Finally, the chaotic system and its observer are implemented using 32-bit microcontrollers. The experimental results confirm good agreement between the responses of the implemented and simulated observers.

scholarly journals A Multiscroll Chaotic Attractors with Arrangement of Saddle-Shapes and Its Field Programmable Gate Array (FPGA) Implementation

Complexity ◽  
2020 ◽  
Vol 2020 ◽  
pp. 1-8
Author(s):  
Faqiang Wang ◽  
Yufang Xiao
Keyword(s):  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Equilibrium Points ◽  
Research Result ◽  
Step Function ◽  
Phase Locked Loops ◽  
Chaotic Attractors ◽  
Digital To Analog Converter ◽  
Field Programmable ◽  
Gate Array

Based on the step function and signum function, a chaotic system which can generate multiscroll chaotic attractors with arrangement of saddle-shapes is proposed and the stability of its equilibrium points is analyzed. The under mechanism for the generation of multiscroll chaotic attractors and the reason for the arrangement of saddle shapes and being symmetric about y-axis are presented, and the rule for controlling the number of scroll chaotic attractors with saddle shapes is designed. Based on the core chips including Altera Cyclone IV EP4CE10F17C8 Field Programmable Gate Array and Digital to Analog Converter chip AD9767, the peripheral circuit and the Verilog Hardware Description Language program for realization of the proposed multiscroll chaotic system is constructed and some experimental results are presented for confirmation. The research result shows that the occupation of multipliers and Phase-Locked Loops in Field Programmable Gate Array is zero.

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

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