A Novel Approach to Radiated Emissions Modeling of Low Voltage Differential Signal on SpaceWire Cable Employing Differential Evolution

2019 ◽  
Author(s):  
Christos D. Nikolopoulos ◽  
Anargyros T. Baklezos ◽  
Christos N. Capsalis
Keyword(s):  
Differential Evolution ◽  
Low Voltage ◽  
Differential Signal ◽  
Emissions Modeling ◽  
Novel Approach ◽  
Radiated Emissions

Verification of Radiated Emissions Modeling for SpaceWire/LVDS Links Routed on CFRP Ground

2020 ◽  
Vol 56 (1) ◽  
pp. 393-402 ◽  
Author(s):  
Christos D. Nikolopoulos ◽  
Anargyros T. Baklezos ◽  
Stylianos Tsatalas ◽  
Christos N. Capsalis
Keyword(s):  
Emissions Modeling ◽  
Radiated Emissions

Novel Approach to Arc Flash Mitigation for Low-Voltage Equipment

2016 ◽  
Vol 52 (6) ◽  
pp. 5262-5270 ◽  
Author(s):  
Raymond Catlett ◽  
Mike Lang ◽  
Steve Scala
Keyword(s):  
Low Voltage ◽  
Novel Approach ◽  
Arc Flash

scholarly journals A High Speed Redundant IO Bus for Energy Power Controller System

2021 ◽  
Vol 2113 (1) ◽  
pp. 012024
Author(s):  
Qinghui Lou ◽  
Liguo Sun ◽  
Haisong Lu ◽  
Weifeng Xu ◽  
Zhebei Wang ◽  
...  
Keyword(s):  
Operating System ◽  
Real Time ◽  
High Throughput ◽  
High Speed ◽  
Low Voltage ◽  
Differential Signal ◽  
Real Time Operating System ◽  
Power Controller ◽  
Data Feedback ◽  
Memory Monitoring

Abstract This paper designs and implements a High Speed Redundant IO Bus for Energy Power Controller System. The physical layer adopts multi-point low-voltage differential signal standard. This bus has the characteristics of high real-time, high throughput and easy expansion. The controller communicates with IO module by A/B bus alternately, monitors link status in real time and collects IO module data. Non real time slots can be used to control non real time messages for IO modules such as time synchronizing and memory monitoring. The controller ARM core runs QNX real-time operating system, and transmits the message needed to communicate with IO modules to the FPGA through DMA. After receiving the message, the FPGA parses the message and automatically fills in the CRC check code and frame end flag at the end of the message. When the FPGA receives the data feedback from the IO module, it performs CRC verification. If the verification passes, it fills the corresponding module receiving buffer. Otherwise, it fills the CRC verification error flag in the register of the corresponding IO module to reduce the load of the arm core.

scholarly journals Chaos Driven Evolutionary Algorithm: a Novel Approach for Optimization

2022 ◽  
Vol 16 ◽  
pp. 21-25
Author(s):  
Roman Senkerik ◽  
Michal Pluhacek ◽  
Zuzana Kominkova Oplatkova
Keyword(s):  
Differential Evolution ◽  
Evolutionary Algorithm ◽  
Chaotic System ◽  
Random Number ◽  
Random Number Generator ◽  
Dissipative System ◽  
Higher Dimensions ◽  
Test Function ◽  
Novel Approach ◽  
Pseudo Random Number Generator

This research deals with the initial investigations on the concept of a chaos-driven evolutionary algorithm Differential evolution. This paper is aimed at the embedding of simple two-dimensional chaotic system, which is Lozi map, in the form of chaos pseudo random number generator for Differential Evolution. The chaotic system of interest is the discrete dissipative system. Repeated simulations were performed on standard benchmark Schwefel’s test function in higher dimensions. Finally, the obtained results are compared with canonical Differential Evolution.

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