A New Technique of Designing Low Power, Low Voltage MOS CML Circuits by using Modifications in the PDN
2003 ◽
Vol 26
(2)
◽
pp. 111-114
◽
Keyword(s):
Keyword(s):
Keyword(s):
2005 ◽
Vol 25
(1_suppl)
◽
pp. S543-S543