A 2.87±0.19dB NF 3.1∼10.6GHz ultra-wideband low-noise amplifier using 0.18µm CMOS technology

Author(s):  
Chia-Hsing Wu ◽  
Yo-Sheng Lin ◽  
Jen-How Lee ◽  
Chien-Chin Wang
2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  


2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
K. Yousef ◽  
H. Jia ◽  
R. Pokharel ◽  
A. Allam ◽  
M. Ragab ◽  
...  

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.


2021 ◽  
Author(s):  
Dongwei Pang ◽  
Yongfeng Gui ◽  
Shiwei Wu ◽  
Xiaohu Wang ◽  
Wang Gang

Author(s):  
Dr. Rashmi S B ◽  
Mr. Raghavendra B ◽  
Mr. Sanketh V

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.


2015 ◽  
Vol 01 (02) ◽  
pp. 68-71
Author(s):  
Neelam Gautam ◽  
◽  
Manish Kumar ◽  
Abhay Chaturvedi ◽  
◽  
...  

Author(s):  
Farshad Shirani Bidabadi ◽  
Sayed Vahid Mir-moghtadaei

In this paper, an Ultra-Wideband (UWB) low noise amplifier (LNA) with low power consumption and high-power gain in 180[Formula: see text]nm CMOS technology is presented. An innovative combination of conventional methods to design UWB-LNA, i.e., resistive-feedback, inductive-series peaking, noise cancelling and inductive degeneration techniques is described here. The proposed LNA consists of two common source amplifiers with resistive feedback in which the noise and power consumption have been reduced by using the noise cancelling and current reuse techniques, respectively. Also, resistive feedback in the first stage reduces input resistance, hereby improving input impedance matching. In the second stage, which is used to increase the power gain, a common source structure with inductive-series peaking and noise cancellation techniques is used. The analytical results agree well with the post layout simulation results. The post-layout simulation shows a gain of [Formula: see text][Formula: see text]dB and noise figure (NF) of 2.3[Formula: see text]dB in the whole [Formula: see text][Formula: see text]dB bandwidth of 0.1[Formula: see text]GHz to 6.1[Formula: see text]GHz, while the S11 and S22 are less than [Formula: see text][Formula: see text]dB. The proposed circuit has a figure of merit of 9.9 which is significantly improved compared to the previous works. The total power dissipation is only 7.3[Formula: see text]mW, and the active area is less than 0.7[Formula: see text]mm2.


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