MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit

This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.

An optimal design of square spiral integrated inductor using metaheuristic techniques

<p>In this paper, the optimal sizing of CMOS RF square spiral integrated inductor utilizing three meta-heuristic techniques namely Ant Colony Optimization, Artificial Bee Colony and Differential Evolution is presented. The π-model is employed for the characterization of inductor behavior. In this optimization procedure, the geometrical parameters of the CMOS RF square spiral integrated inductor are considered as the design variables that satisfy the most important constraints such as the fixed value of required inductance 4nH at the operating frequency 2.4 GHz. The design of the integrated square spiral inductor is done with UMC 130 nm CMOS technology. A comparison between the used meta-heuristic techniques is emphasized. The optimization results are checked and validated by the mean of the Momentum Advanced Design System (ADS).</p>

A Novel Harmonic Suppression Traction Transformer with Integrated Filtering Inductors for Railway Systems

This study analyzes and evaluates the feasibility of a harmonic suppression traction transformer (HSTT) for harmonic reduction in railway systems. This new type of transformer can improve the power quality of railway systems by preventing high-frequency harmonic currents from injecting into the traction grid. As the physical size of available space in high-speed trains is strictly limited, low space-occupying filtering techniques are needed. Therefore, an HSTT with integrated filtering inductors (IFIs) capable of being implemented in regular trains is proposed. Taking advantage of the HSTT, a specially constructed inductive-capacitive-inductive (LCL)-type filter is used for harmonic suppression instead of a regular LCL-type filter. The proposed filter is composed of an integrated inductor, leakage inductor of the traction transformer, and an external filter capacitor. In this paper, we analyze the topology of the proposed system, construct a mathematical model to reveal the magnetic decoupling theory of IFIs, and discuss the design and calculation procedures of the HSTT with IFIs. The field circuit coupling simulation of the HSTT with IFIs is performed to validate the effectiveness of the proposed system. Finally, the practical operation based on a 10 kVA prototype shows that the proposed scheme can not only suppress the high-order frequency harmonics but also decrease the installed space of filter devices.