10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation

2015 ◽  
Author(s):  
Luhao Wang ◽  
Alireza Shafaei ◽  
Shuang Chen ◽  
Yanzhi Wang ◽  
Shahin Nazarian ◽  
...  
Keyword(s):  
Process Variation ◽  
Cross Layer ◽  
Gate Length ◽  
Sram Design

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry

2019 ◽  
Vol 29 (06) ◽  
pp. 2050095
Author(s):  
Chua-Chin Wang ◽  
Zong-You Hou ◽  
Deng-Shian Wang ◽  
Chia-Lung Hsieh
Keyword(s):  
Power Supply ◽  
Process Variation ◽  
Half Period ◽  
Clock Rate ◽  
System Clock ◽  
Sram Cell ◽  
Sram Design ◽  
Measurement Results ◽  
Power Delay Product ◽  
28 Nm

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

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