Finding double Euler trails of planar graphs in linear time [CMOS VLSI circuit design]

2003 ◽  
Author(s):  
Zhi-Zhong Chen ◽  
Xin He ◽  
Chun-Hsi Huang
Keyword(s):  
Circuit Design ◽  
Planar Graphs ◽  
Linear Time ◽  
Vlsi Circuit ◽  
Cmos Vlsi

A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

2000 ◽  
Vol 47 (1) ◽  
pp. 129-140 ◽  
Author(s):  
Yungseon Eo ◽  
W.R. Eisenstadt ◽  
Ju Young Jeong ◽  
Oh-Kyong Kwon
Keyword(s):  
Circuit Design ◽  
Experimental Verification ◽  
Vlsi Circuit ◽  
On Chip ◽  
Cmos Vlsi

Sensitivity-based CMOS VLSI circuit performance optimisation

1995 ◽  
Vol 31 (22) ◽  
pp. 1918-1919
Author(s):  
P.J. Mather ◽  
P. Hallam ◽  
M. Brouwer
Keyword(s):  
Vlsi Circuit ◽  
Circuit Performance ◽  
Cmos Vlsi

scholarly journals Linear-Time Succinct Encodings of Planar Graphs via Canonical Orderings

1999 ◽  
Vol 12 (3) ◽  
pp. 317-325 ◽  
Author(s):  
Xin He ◽  
Ming-Yang Kao ◽  
Hsueh-I Lu
Keyword(s):  
Planar Graphs ◽  
Linear Time
Sign in / Sign up

Export Citation Format

Share Document