Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories
Keyword(s):
2012 ◽
Vol 20
(7)
◽
pp. 1221-1234
◽
2017 ◽
Vol E100.A
(2)
◽
pp. 653-662
Keyword(s):
2012 ◽
Vol 20
(12)
◽
pp. 2302-2314
◽
2010 ◽
Vol E93-C
(3)
◽
pp. 317-323
◽
Keyword(s):
2011 ◽
Vol E94-C
(4)
◽
pp. 539-547
◽
Keyword(s):