A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories

Digest of Technical Papers., Symposium on VLSI Circuits. ◽

10.1109/vlsic.1995.520689 ◽

2002 ◽

Author(s):

K. Takeuchi ◽

T. Tanaka ◽

H. Nakamura

Keyword(s):

Flash Memories ◽

Array Architecture ◽

Multi Level ◽

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A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories

IEEE Journal of Solid-State Circuits ◽

10.1109/4.499738 ◽

1996 ◽

Vol 31 (4) ◽

pp. 602-609 ◽

Author(s):

K. Takeuchi ◽

T. Tanaka ◽

H. Nakamura

Keyword(s):

Flash Memories ◽

Array Architecture ◽

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Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

2006 IEEE Workshop on Signal Processing Systems Design and Implementation ◽

10.1109/sips.2006.352599 ◽

2006 ◽

Author(s):

Wei Liu ◽

Junrye Rho ◽

Wonyong Sung

Keyword(s):

Low Power ◽

Error Correction ◽

High Throughput ◽

Vlsi Design ◽

Flash Memories ◽

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A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories

Symposium on VLSI Circuits ◽

10.1109/vlsic.1997.623810 ◽

1997 ◽

Author(s):

Takeuchi ◽

Tanaka ◽

Tanzawa

Keyword(s):

Flash Memories ◽

Cell Architecture ◽

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Comparison of TID response and SEE characterization of single- and multi-level high density NAND flash memories

2009 European Conference on Radiation and Its Effects on Components and Systems ◽

10.1109/radecs.2009.5994731 ◽

2009 ◽

Author(s):

Farokh Irom ◽

Duc N. Nguyen ◽

Reno Harboe-Sorensen ◽

Ari Virtanen

Keyword(s):

High Density ◽

Flash Memories ◽

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A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories

2010 Proceedings of ESSCIRC ◽

10.1109/esscirc.2010.5619799 ◽

2010 ◽

Author(s):

T. Tanzawa ◽

T. Tanaka ◽

S. Tamada ◽

J. Kishimoto ◽

S. Yamada ◽

...

Keyword(s):

Temperature Compensation ◽

Flash Memories ◽

Line Voltage ◽

Voltage Generator ◽

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Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding

2019 19th International Symposium on Communications and Information Technologies (ISCIT) ◽

10.1109/iscit.2019.8905168 ◽

2019 ◽

Author(s):

Duc-Phuc Nguyen ◽

Khoa Le ◽

Fakhreddine Ghaffari ◽

David Declercq

Keyword(s):

Performance Enhancement ◽

Polar Codes ◽

Flash Memories ◽

Multi Level ◽

Systematic Encoding

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Evaluation of Mechanisms in TID Degradation and SEE Susceptibility of Single- and Multi-Level High Density NAND Flash Memories

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2011.2161885 ◽

2011 ◽

Vol 58 (5) ◽

pp. 2477-2482 ◽

Author(s):

Farokh Irom ◽

Duc N. Nguyen ◽

Reno Harboe-Sorensen ◽

Ari Virtanen

Keyword(s):

High Density ◽

Flash Memories ◽

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A Heavy-ion Beam Monitor Based on 3D NAND Flash Memories

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2021.3072298 ◽

2021 ◽

pp. 1-1

Author(s):

S. Gerardin ◽

M. Bagatin ◽

A. Paccagnella ◽

S. Beltrami ◽

A. Costantino ◽

...

Keyword(s):

Ion Beam ◽

Heavy Ion ◽

Flash Memories ◽

Beam Monitor ◽

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Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure

Japanese Journal of Applied Physics ◽

10.7567/jjap.53.064306 ◽

2014 ◽

Vol 53 (6) ◽

pp. 064306 ◽

Author(s):

Ju Tae Ryu ◽

Sung Hwan Jang ◽

Tae Whan Kim

Keyword(s):

Electrical Characteristics ◽

Dielectric Structure ◽

Coupling Ratio ◽

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Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

Japanese Journal of Applied Physics ◽

10.1143/jjap.48.04c062 ◽

2009 ◽

Vol 48 (4) ◽

pp. 04C062 ◽

Author(s):

Myounggon Kang ◽

Ki-Tae Park ◽

Youngsun Song ◽

Soonwook Hwang ◽

Byung Yong Choi ◽

...

Keyword(s):

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