Crosstalk-aware TSV-buffer Insertion in 3D IC

2019 32nd IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc46988.2019.1570539111 ◽

2019 ◽

Author(s):

Yen-Hao Chen ◽

Po-Chen Huang ◽

Fu-Wei Chen ◽

Allen C.-H. Wu ◽

TingTing Hwang

Keyword(s):

Buffer Insertion ◽

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Performance optimization and power efficiency in 3D IC with buffer insertion scheme

2016 29th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2016.7905473 ◽

2016 ◽

Author(s):

Mohammad A Ahmed ◽

Sucheta Mohapatra ◽

Malgorzata Chrzanowska-Jeske

Keyword(s):

Performance Optimization ◽

Power Efficiency ◽

Buffer Insertion ◽

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Buffer Insertion for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_3 ◽

2012 ◽

pp. 75-97

Author(s):

Sung Kyu Lim

Keyword(s):

Buffer Insertion ◽

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TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

IEICE Transactions on Electronics ◽

10.1587/transele.e95.c.1864 ◽

2012 ◽

Vol E95.C (12) ◽

pp. 1864-1871 ◽

Author(s):

Hung Viet NGUYEN ◽

Myunghwan RYU ◽

Youngmin KIM

Keyword(s):

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Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511123 ◽

2007 ◽

Author(s):

Sherif A. Tawfik ◽

Volkan Kursun

Keyword(s):

Power Consumption ◽

Distribution Networks ◽

Transition Time ◽

Gradual Transition ◽

Clock Distribution ◽

Buffer Insertion ◽

Time Relaxation ◽

Clock Distribution Networks ◽

Reduced Power Consumption

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A TSV-Last Approach for 3D-IC Integration and Packaging using WNi Platable Barrier Layer

2021 IEEE 71st Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc32696.2021.00060 ◽

2021 ◽

Author(s):

Murugesan Mariappan ◽

Kiyoharu Mori ◽

Mitsumasa Koyanagi ◽

Takafumi Fukushima

Keyword(s):

Barrier Layer ◽

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A Programmable Checker for Automated 2.5D/3D IC ESD Verification

IEEE Transactions on Components Packaging and Manufacturing Technology ◽

10.1109/tcpmt.2020.3039608 ◽

2020 ◽

pp. 1-1

Author(s):

Dina Medhat ◽

Mohamed Dessouky ◽

Diaa Eldin Khalil

Keyword(s):

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A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

2021 22nd International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed51717.2021.9424282 ◽

2021 ◽

Author(s):

Sachin Bhat ◽

Sounak Shaun Ghosh ◽

Sourabh Kulkarni ◽

Mingyu Li ◽

Csaba Andras Moritz

Keyword(s):

3D Ic ◽

Wafer Scale ◽

Fine Grained ◽

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Thermal-mechanical performance analysis and structure optimization of the TSV in 3D IC

IEEE Transactions on Components Packaging and Manufacturing Technology ◽

10.1109/tcpmt.2021.3062031 ◽

2021 ◽

pp. 1-1

Author(s):

Guigen Ye ◽

Zhimin Wang ◽

Xinjian Li ◽

Shifeng Xue ◽

Liang Gong

Keyword(s):

Performance Analysis ◽

Mechanical Performance ◽

Structure Optimization ◽

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Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs

Proceedings of the 2014 on International symposium on physical design - ISPD '14 ◽

10.1145/2560519.2560531 ◽

2014 ◽

Author(s):

Shreepad Panth ◽

Kambiz Samadi ◽

Yang Du ◽

Sung Kyu Lim

Keyword(s):

3D Ic ◽

Congestion Mitigation

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Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking

2011 IEEE 61st Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2011.5898537 ◽

2011 ◽

Author(s):

Yu-Min Lin ◽

Chau-Jie Zhan ◽

Jing-Ye Juang ◽

John H. Lau ◽

Tai-Hong Chen ◽

...

Keyword(s):

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