An Efficient CRT-based Bit-parallel Multiplier for Special Pentanomials

2021 ◽  
pp. 1-1
Author(s):  
Yin Li ◽  
Xinyuan Cui ◽  
Yu Zhang
Keyword(s):  
VLSI Design ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-7 ◽  
Author(s):  
Yin Li ◽  
Yu Zhang ◽  
Xiaoli Guo

Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that related Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA), which leads to a highly efficient Karatsuba multiplier. In this paper, we consider a new special class of irreducible trinomial, namely, xm+xm/3+1. Based on a three-term KA and shifted polynomial basis (SPB), a novel bit-parallel multiplier is derived with better space and time complexity. As a main contribution, the proposed multiplier costs about 2/3 circuit gates of the fastest multipliers, while its time delay matches our former result. To the best of our knowledge, this is the first time that the space complexity bound is reached without increasing the gate delay.


1988 ◽  
Vol 37 (3) ◽  
pp. 274-282 ◽  
Author(s):  
S. Nakamura ◽  
K.-Y. Chu

Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.


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