Stereo: Assignment and Scheduling in MPSoC under Process Variation by Combining Stochastic and Decomposition Approaches

2022 ◽  
pp. 1-1
Behnam Khodabandehloo ◽  
Ahmad Khonsari ◽  
Payman Behnam ◽  
Alireza Majidi ◽  
Mohammad Hajiesmaili
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

2020 ◽  
pp. 1-1
Zhengxing Zhang ◽  
Sally I. El-Henawy ◽  
Allan Sadun ◽  
Ryan Miller ◽  
Luca Daniel ◽  

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

2014 ◽  
Vol 10 (1) ◽  
pp. 19-27 ◽  
En-Hua Ma ◽  
Wen-En Wei ◽  
Hung-Yi Li ◽  
James Chien-Mo Li ◽  
I-Chun Cheng ◽  

Sign in / Sign up

Export Citation Format

Share Document