LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

The circuit changes the threshold voltage effectively with a definite delay and power by altering the body biasing of the transistors. The body bias is employed to govern the frequency and leakage of the memory device. The threshold voltage of individual transistor is decreases by applying the reverse body bias (RBB) and increases with forward body bias (FBB). This paper presents the viability of RBB to decrease the leakage power and increase in the speed of operations for SRAM circuit. The investigation of RBB dependencies on various performance parameters are analyzed. It is observed that the leakage power improves by 30.32% on applying RBB voltage compared to zero body bias while the transient power increases by 3.22% but decrease of delay by 84.56% dominates on it. Because of this the overall energy consumption reduces by 84.06%. Further the simulation work is carried out to see effect of supply voltage variation on leakage power at different RBB voltage and temperature. Therefore, the RBB scheme is beneficial for devices of low leakage, low energy and high speed of operation but this RBB voltage is limited by band-to-band tunneling current.


2008 ◽  
Vol 17 (06) ◽  
pp. 1111-1128 ◽  
Author(s):  
DAVID WOLPERT ◽  
PAUL AMPADU

Temperature and voltage fluctuations affect delay sensitivity differently, as supply voltage is reduced. These differences make runtime variations particularly difficult to manage in dynamic voltage scaling systems, which adjust supply voltage in accordance with the required operating frequency. To include process variation in current table-lookup methods, a worst-case process is typically assumed. We propose a new method that takes process variation into account and reduces the excessive runtime variation guardbands. Our approach uses a ring oscillator to generate baseline frequencies, and employs a guardband lookup table to offset this baseline. The new method ensures robust operation and reduces power consumption by up to 20% compared with a method that assumes worst-case process variation in filling a lookup table.


2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.


2015 ◽  
Vol 51 (17) ◽  
pp. 1322-1324 ◽  
Author(s):  
Seung‐Tae Kim ◽  
Oh‐Kyong Kwon

Author(s):  
Jian-Ming Wu ◽  
Yan-Tsang Lin ◽  
Yuan-Chih Lin ◽  
Min-Lang Yang

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