Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient Dynamic Thermal Management

2010 ◽  
Vol 29 (10) ◽  
pp. 1586-1599 ◽  
Author(s):  
Shervin Sharifi ◽  
Tajana Šimunić Rosing
Keyword(s):  
Thermal Management ◽  
Temperature Sensing ◽  
Dynamic Thermal Management ◽  
Chip Temperature ◽  
On Chip

Analysis of Thermal Properties of Power Multifinger HEMT Devices

2018 ◽  
Author(s):  
Aleš Chvála ◽  
Robert Szobolovszký ◽  
Jaroslav Kováč ◽  
Martin Florovič ◽  
Juraj Marek ◽  
...  
Keyword(s):  
Temperature Distribution ◽  
Thermal Management ◽  
High Electron Mobility Transistor ◽  
Structure Design ◽  
High Electron ◽  
Design And Optimization ◽  
Chip Temperature ◽  
Materials Used ◽  
On Chip ◽  
Measurement Approach

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

2014 ◽  
pp. 368-398
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Task Mapping ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
Management Measures ◽  
Mapping Process ◽  
On Chip ◽  
And Task

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

Performance Analysis of Temperature Management Approaches in Networks-on-Chip

2012 ◽  
Vol 3 (4) ◽  
pp. 19-41
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Large Scale ◽  
Negative Impact ◽  
Temperature Management ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
System Integrity ◽  
On Chip

With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.

Temperature Sensor Allocation Strategy and Full Thermal Reconstruction for Microprocessors

2013 ◽  
Vol 380-384 ◽  
pp. 2986-2989
Author(s):  
Xin Li ◽  
Meng Tian Rong
Keyword(s):  
Thermal Management ◽  
Thermal Gradient ◽  
Gradient Analysis ◽  
Hot Spot ◽  
Temperature Sensors ◽  
Thermal Sensors ◽  
Dynamic Thermal Management ◽  
Effective Strategies ◽  
Management Techniques ◽  
On Chip

On-chip thermal sensors are employed by dynamic thermal management techniques to measure runtime thermal behavior of microprocessors so as to prevent the on-set of high temperatures. The allocation and the placement of thermal sensors directly impact the effectiveness of the dynamic thermal management mechanisms. In this paper, we propose systematic and effective strategies for determining the optimal locations for temperature sensors based on thermal gradient analysis to provide the trade-off between hot spot estimation and full thermal reconstruction. Experimental results indicate the superiority of our techniques and confirm that our proposed methods are able to create a sensor distribution for a given microprocessor architecture.

Dynamic Thermal Management for system-on-chip using bus arbitration

2010 ◽  
Author(s):  
K. Srivathsa Sudheendra ◽  
B. Suresh Vikram ◽  
Pavan Panchapakeshan ◽  
Sandip Kundu
Keyword(s):  
Thermal Management ◽  
System On Chip ◽  
Dynamic Thermal Management ◽  
Bus Arbitration ◽  
On Chip
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