Analysis of Thermal Properties of Power Multifinger HEMT Devices

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

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Advanced Characterization Techniques and Analysis of Thermal Properties of AlGaN/GaN Multifinger Power HEMTs on SiC Substrate Supported by Three-Dimensional Simulation

Journal of Electronic Packaging ◽

10.1115/1.4043477 ◽

2019 ◽

Vol 141 (3) ◽

Cited By ~ 2

Author(s):

Aleš Chvála ◽

Robert Szobolovszký ◽

Jaroslav Kováč ◽

Martin Florovič ◽

Juraj Marek ◽

...

Keyword(s):

Temperature Distribution ◽

Three Dimensional ◽

High Electron Mobility Transistor ◽

Advanced Characterization ◽

Structure Design ◽

Operating Conditions ◽

High Electron ◽

Individual Layer ◽

Materials Used ◽

On Chip

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN-based high-electron mobility transistor (HEMT) grown on a SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. The second approach utilizes electrical I–V characteristics of the Schottky diode neighboring to the heat source of the active transistor under different dissipated power for temperature measurement. These methods are further verified by measurements with microthermistors. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from the temperature distribution in the structure with the support of three-dimensional thermal simulation of the device. Thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The influence of individual layer properties on the thermal performance of different HEMT structures under different operating conditions is presented. The results show that the proposed experimental methods supported by simulation have a potential for the design, analysis, and thermal management of HEMT.

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Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Advancing Embedded Systems and Real-Time Communications with Emerging Technologies ◽

10.4018/978-1-4666-6034-2.ch015 ◽

2014 ◽

pp. 368-398

Author(s):

Tim Wegner ◽

Martin Gag ◽

Dirk Timmermann

Keyword(s):

Thermal Management ◽

System Performance ◽

Task Mapping ◽

Systematic Analysis ◽

Networks On Chip ◽

Chip Temperature ◽

Management Measures ◽

Mapping Process ◽

On Chip ◽

And Task

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

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A wideband cryogenic microwave low-noise amplifier

Beilstein Journal of Nanotechnology ◽

10.3762/bjnano.11.131 ◽

2020 ◽

Vol 11 ◽

pp. 1484-1491

Author(s):

Boris I Ivanov ◽

Dmitri I Volkhin ◽

Ilya L Novikov ◽

Dmitri K Pitsun ◽

Dmitri O Moskalev ◽

...

Keyword(s):

Power Dissipation ◽

Coplanar Waveguide ◽

Noise Temperature ◽

High Electron Mobility Transistor ◽

Low Noise ◽

High Electron ◽

Frequency Range ◽

Noise Amplifier ◽

On Chip

A broadband low-noise four-stage high-electron-mobility transistor amplifier was designed and characterized in a cryogen-free dilution refrigerator at the 3.8 K temperature stage. The obtained power dissipation of the amplifier is below 20 mW. In the frequency range from 6 to 12 GHz its gain exceeds 30 dB. The equivalent noise temperature of the amplifier is below 6 K for the presented frequency range. The amplifier is applicable for any type of cryogenic microwave measurements. As an example we demonstrate here the characterization of the superconducting X-mon qubit coupled to an on-chip coplanar waveguide resonator.

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Simplified Thermal Model of Silicon Thermoelectric Microcooler for On-Chip Hot Spot Remediation

ASME 2007 InterPACK Conference, Volume 2 ◽

10.1115/ipack2007-33940 ◽

2007 ◽

Cited By ~ 1

Author(s):

Peng Wang ◽

Avram Bar-Cohen

Keyword(s):

Thermal Management ◽

Material Properties ◽

Hot Spots ◽

Hot Spot ◽

Design Tool ◽

The Novel ◽

Thermo Electric ◽

Design And Optimization ◽

Conventional Cooling ◽

On Chip

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.

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Performance Analysis of Temperature Management Approaches in Networks-on-Chip

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/jertcs.2012100102 ◽

2012 ◽

Vol 3 (4) ◽

pp. 19-41

Author(s):

Tim Wegner ◽

Martin Gag ◽

Dirk Timmermann

Keyword(s):

Thermal Management ◽

System Performance ◽

Large Scale ◽

Negative Impact ◽

Temperature Management ◽

Systematic Analysis ◽

Networks On Chip ◽

Chip Temperature ◽

System Integrity ◽

On Chip

With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.

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