Thermal Characteristics and Thermomechanical Reliability of Board-Level Stacked-Die Packages Subjected to Coupled Power and Thermal Cycling Test

2008 ◽  
Vol 31 (2) ◽  
pp. 495-502 ◽  
Author(s):  
Tong Hong Wang ◽  
Chang-Chi Lee ◽  
Yi-Shao Lai ◽  
Yu-Cheng Lin
Keyword(s):  
Thermal Cycling ◽  
Thermal Characteristics ◽  
Thermal Cycling Test ◽  
Cycling Test ◽  
Thermomechanical Reliability ◽  
Board Level

Development of BiAgX® HT Solder Paste for 200°C Application

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000128-000133 ◽  
Author(s):  
Hongwen Zhang ◽  
Jonathan Minter ◽  
Ning-Cheng Lee
Keyword(s):  
Shear Strength ◽  
Thermal Cycling ◽  
Melting Temperature ◽  
Thermal Aging ◽  
Joint Strength ◽  
Solder Paste ◽  
Thermal Cycling Test ◽  
Cycling Test ◽  
Die Attach ◽  
Board Level

Abstract BiAgX® paste with the remelting temperature around 262°C has been tested and adopted successfully for die attach applications [1–5]. BiAgX® HT pastes with the enhanced remelting temperature above 265°C have been designed for the application of 200°C or even higher. The joint strength has been well maintained for most of the tested pastes after thermal aging @ 200°C for 1000hrs. The thermal cycling test (from −55°C to 200°C) degrades the bond shear strength but some of the tested pastes can still keep the joint strength well above IEC standard (IEC 60749-19) required. The melting temperature and the reliability have been observed to closely associate with the alloying elements Z%wt. The BiAgX® pastes have also been modified for board level assembly application. BiAgX® solder wire is under development too.

Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions

2005 ◽  
Vol 128 (3) ◽  
pp. 281-284 ◽  
Author(s):  
Tong Hong Wang ◽  
Chang-Chi Lee ◽  
Yi-Shao Lai ◽  
Yu-Cheng Lin
Keyword(s):  
Thermal Analysis ◽  
Boundary Conditions ◽  
Thermal Cycling ◽  
Thermal Cycling Test ◽  
Transient Thermal Analysis ◽  
Cycling Test ◽  
Test Conditions ◽  
Power Cycling ◽  
Transient Thermal ◽  
Board Level

In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.

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