Effect of rapid thermal shock cycle on the thermomechanical reliability of 20Sn-80Pb solder bumps

The influence of rapid thermal shock(RTS) cycles on 20Sn-80Pb solder bumps was studied. In the study, 20Sn-80Pb solder bumps were prepared by desktop nitrogen lead-free reflow soldering machine. The prepared 20Sn-80Pb solder bumps were used for RTS test in the temperature rang of 0°C ~ 150°C. One cycle of RTS is 24 seconds, and the temperature rise and fall rate of RTS is 12.5 C/s. The result indicated that when the cycle of RTS reached 1500T (here T is cycle, the same below), the shear strength of Sn-80Pb solder bump dropped by drastically 48.6%. Whereas, when the cycle of RTS reached 5500T, 20Sn-80Pb solder bumps’ shear strength decreased to 18.35 MPa, which increased by 7.5% compared with that of l6.97 MPa at 4500T. With the increase of RTS cycles, 20Sn-80Pb solder bumps’ shear strength was a decreasing trend and the fracture mechanism changed from ductile fracture to ductile-brittle mixed fracture, which could be subject to the thickening of the interfaical IMCs and the stress concentration caused by the growth of interfacial IMCs. To understand the changes of the mechanical properties of 20Sn-80Pb solder bumps, the influences of RTS on the crack and interfacial IMC of 20Sn-80Pb solder bumps were studied in details.

Design for Reliability of Automotive Chip Scale Packages by Calibrated Virtual Prototyping

The thermomechanical reliability of the package and interconnections of assembled flip chip ball grid arrays (FC-BGA) is investigated in comparison to a reference chip scale package (CSP). Comparison is made using finite element (FE-) simulation. A combined measuring-simulation technique is applied to calibrate the finite element simulations on a reference object. Adjustment is made based on the in-plane deformation field evaluated by both simulation and optical measurement. For the latter an optical sensor for in-plane deformation and strain field analysis is used based on grey scale correlation method. A methodology is presented and to extrapolate the knowledge gained to alternative package types of different but similar design in order to evaluate their suitability for the desired application before the physical fabrication (virtual prototyping).

Structures and Materials of System in Package: A Review

Background: As a new type of advanced packaging and system integration technology, System-in-Package (SiP) can realize the miniaturization and multi-functionalization of electronic products and is listed as an important direction of development by International Technology Roadmap for Semiconductors (ITRS). <P> Objective: This paper mainly introduces and discusses recent academic research and patents on package structure and packaging materials. Additionally, the trending of development is described. <P> Methods: Firstly, we analyze and summarize the challenges and existing problems in SiP. Then the corresponding solutions are introduced with respect to packaging structure and packaging materials. Finally, the research status of SIP and some patents in these aspects is reviewed. <P> Results: In order to increase the density of internal components, SiP products need to use a stacked structure. The cause of different performance in SiP products are: 1) the stress concentration and bonding quality problems caused by the chip stack structure; 2) the warpage and package thickness problems caused by the package stack; 3) Thermal conductivity of materials and thermal mismatch between materials; 4) Dielectric properties and thermomechanical reliability of materials. The following solutions are summarized: 1) Structural optimization of chip stacking and packaging stacking; 2) Application of new packaging technology; 3) Optimization of packaging materials; 4) Improvement of packaging material processing technology. <P> Conclusion: With the study of packaging structure and packaging materials, SiP can meet the requirements of the semiconductor industry and have great future prospects