Monolithic Wafer-Level Rectangular Waveguide and Its Transition to Coplanar Waveguide Line Using a Simplified 3-D Fabrication Process

Author(s):  
Nahid Vahabisani ◽  
Mojgan Daneshmand
Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2605
Author(s):  
Ashley Novais ◽  
Carlos Calaza ◽  
José Fernandes ◽  
Helder Fonseca ◽  
Patricia Monteiro ◽  
...  

Multisite neural probes are a fundamental tool to study brain function. Hybrid silicon/polymer neural probes combine rigid silicon and flexible polymer parts into one single device and allow, for example, the precise integration of complex probe geometries, such as multishank designs, with flexible biocompatible cabling. Despite these advantages and benefiting from highly reproducible fabrication methods on both silicon and polymer substrates, they have not been widely available. This paper presents the development, fabrication, characterization, and in vivo electrophysiological assessment of a hybrid multisite multishank silicon probe with a monolithically integrated polyimide flexible interconnect cable. The fabrication process was optimized at wafer level, and several neural probes with 64 gold electrode sites equally distributed along 8 shanks with an integrated 8 µm thick highly flexible polyimide interconnect cable were produced. The monolithic integration of the polyimide cable in the same fabrication process removed the necessity of the postfabrication bonding of the cable to the probe. This is the highest electrode site density and thinnest flexible cable ever reported for a hybrid silicon/polymer probe. Additionally, to avoid the time-consuming bonding of the probe to definitive packaging, the flexible cable was designed to terminate in a connector pad that can mate with commercial zero-insertion force (ZIF) connectors for electronics interfacing. This allows great experimental flexibility because interchangeable packaging can be used according to experimental demands. High-density distributed in vivo electrophysiological recordings were obtained from the hybrid neural probes with low intrinsic noise and high signal-to-noise ratio (SNR).


2007 ◽  
Vol 4 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Qing Liu ◽  
Patrick Fay ◽  
Gary H. Bernstein

Quilt Packaging (QP), a novel chip-to-chip communication paradigm for system-in-package integration, is presented. By forming protruding metal nodules along the edges of the chips and interconnecting integrated circuits (ICs) through them, QP offers an approach to ameliorate the I/O speed bottleneck. A fabrication process that includes deep reactive ion etching, electroplating, and chemical-mechanical polishing is demonstrated. As a low-temperature process, it can be easily integrated into a standard IC fabrication process. Three-dimensional electromagnetic simulations of coplanar waveguide QP structures have been performed, and geometries intended to improve impedance matching at the interface between the on-chip interconnects and the chip-to-chip nodule structures were evaluated. Test chips with 100 μm wide nodules were fabricated on silicon substrates, and s-parameters of chip-to-chip interconnects were measured. The insertion loss of the chip-to-chip interconnects was as low as 0.2 dB at 40 GHz. Simulations of 20 μm wide QP structures suggest that the bandwidth of the inter-chip nodules is expected to be above 200 GHz.


2019 ◽  
Vol 12 (5) ◽  
pp. 367-371
Author(s):  
Yibang Wang ◽  
Xingchang Fu ◽  
Aihua Wu ◽  
Chen Liu ◽  
Peng Luan ◽  
...  

AbstractWe present details of on-wafer-level 16-term error model calibration kits used for the characterization of W-band circuits based on a grounded coplanar waveguide (GCPW). These circuits were fabricated on a thin gallium arsenide (GaAs) substrate, and via holes, were utilized to ensure single mode propagation (i.e., eliminating the parallel-plate mode or surface mode). To ensure the accuracy of the definition for the calibration kits, multi-line thru-reflect-line (MTRL) assistant standards were also fabricated on the same wafer and measured. The same wafer also contained passive and active devices, which were measured subject to both 16-term and conventional line-reflect-reflect-match calibrations. Measurement results show that 16-term calibration kits are capable of determining the cross-talk more accurately. Other typical calibration techniques were also implemented using the standards on the GCPW calibration kits, and were compared with the MTRL calibration using a passive device under test. This revealed that the proposed GCPW GaAs calibration substrate could be a feasible alternative to conventional CPW impedance standard substrates, for on-wafer measurements at W-band and above.


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