A CMOS Integrator-Based Clock-Free Time-to-Digital Converter for Home-Monitoring LiDAR Sensors

This paper presents a nine-bit integrator-based time-to-digital converter (I-TDC) realized in a 180 nm CMOS technology for the applications of indoor home-monitoring light detection and ranging (LiDAR) sensors. The proposed I-TDC exploits a clock-free configuration so as to discard clock-related dynamic power consumption and some notorious issues such as skew, glitch, and synchronization. It consists of a one-dimensional (1D) flash TDC to generate coarse-control codes and an integrator with a peak detection and hold (PDH) circuit to produce fine-control codes. A thermometer-to-binary converter is added to the 1D flash TDC, yielding four-bit coarse codes so that the measured detection range can be represented by nine-bit digital codes in total. Test chips of the proposed I-TDC demonstrate the measured results of the 53 dB dynamic range, i.e., the maximum detection range of 33.6 m and the minimum range of 7.5 cm. The chip core occupies the area of 0.14 × 1.4 mm2, with the power dissipation of 1.6 mW from a single 1.2-V supply.

Design, Application, and Verification of the Novel SEU Tolerant Abacus-Type Layouts

Radiation tolerance improvements for advanced technologies have attracted considerable interests in space application. In this paper, the single event upset (SEU) hardened double interlocked storage cell (DICE) D-type flip-flops (DFFs) with abacus-type time-delay cell are proposed and successfully implemented in our test chips. The layout structures of two kinds of abacus-type time-delay cells are illustrated, and their hardening effectiveness are verified by our simulations and heavy ion irradiations. The systematic heavy ion experimental results show that the applied abacus-type time-delay cells can reduce the SEU cross sections of DICE DFFs significantly, and even the SEU immune is observed for the full “0” data pattern. Besides, an apparent test mode dependency of the abacus-type hardened circuits is also observed. The results indicate that the nanoscale abacus structure may be suitable for space application in harsh radiation environment.

Automated Linescan Analysis for CMP Modeling

Many of the process steps used in semiconductor chip manufacturing require planar (smooth) surfaces on the wafer to ensure correct pattern printing and generation of multilevel interconnections in the chips during manufacturing. Chemical-mechanical polishing/planarization (CMP) is the primary process used to achieve these surface planarity requirements. Modeling of CMP processes allows users to detect and fix large surface planarity variations (hotspots) in the layout prior to manufacturing. Fixing hotspots before tape-out may significantly reduce turnaround time and the cost of manufacturing. Creating an accurate CMP model that takes into account complicated chemical and mechanical polishing mechanisms is challenging. Measured data analysis and extraction of erosion and dishing data from profile linescans from test chips are important steps in CMP model building. Measured linescans are often tilted and noisy, which makes the extraction of erosion and dishing data more difficult. The development and implementation of algorithms used to perform automated linescan analysis may significantly reduce CMP model building time and improve the accuracy of the models. In this work, an automated linescan analysis (ALSA) tool is presented that performs automated linescan delineation, test pattern separation, and automatic extraction of erosion and dishing values from linescan data.

A Study on the Pattern Effects of Chemical Mechanical Planarization with CNN-Based Models

Chemical mechanical polishing (CMP) has become one of the most important process stages in the fabrication of advanced integrated circuits (IC). The CMP pattern effect strongly influences the planarization of the chip surface morphology after CMP, degrading the performance and the yield of the circuits. In this paper, we introduce a method to predict the post-CMP surface morphology with a convolutional neural network (CNN)-based CMP model. Then, CNN-based, density step height (DSH)-based, and common neural-network-based CMP models are built to compare the accuracy of the predictions. The test chips are designed and taped out and the predictions of the three models are compared with experimental results measured by an atomic force profiler (AFP) and scanning electron microscope (SEM). The results show that CNN-based CMP models have better accuracy by taking advantage of the CNN networks to extract features from images instead of the traditional equivalent pattern parameters. The effective planarization length (EPL) is introduced and defined to make better predictions with real-time CMP models and in dummy filling tasks. Experiments are designed to show a method to solve the EPL.

БЛОКИ КОЛЬЦЕВЫХ ГЕНЕРАТОРОВ ДЛЯ ИССЛЕДОВАНИЯ РАДИАЦИОННЫХ ПАРАМЕТРОВ И АТТЕСТАЦИИ БИБЛИОТЕК ЭЛЕМЕНТОВ НАНОМЕТРОВЫХ КМОП СБИС СНК

Разработан набор блоков кольцевых генераторов (КГ) в составе тестовых кристаллов (ТК) для расчетно-экспериментальной оценки радиационной стойкости нанометровых (суб-100 нм) КМОП СБИС типа «система на кристалле» (СнК). Показано, что результаты исследования КГ позволяют расчетно-экспериментальными методами прогнозировать радиационную стойкость СБИС, в частности, при воздействии отдельных ядерных частиц (ОЯЧ). A set of ring oscillator (RO) blocks has been designed and implemented in test chips for further experiment-based SoC radiation hardness calculation. It has been shown that the results of the RO tests allow using experimental methods to predict SoC radiation hardness, in particular, on exposure to heavy particles.

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.