An I/O Coupling Multiplier Circuit and Its Application to Wideband Filters and Diplexers

Abstract This paper presents a radio frequency (RF) energy harvesting (RFEH) system with a multiband antenna configuration that can simultaneously harvest energy from the sub-6 GHz and 5G millimeter-wave (mm-Wave) frequency bands. The performance of the RFEH system is studied from −25 dBm to 5 dBm input power levels underlying the maximization of the overall efficiency and possible optimization strategies. The maximum achievable power conversion efficiency (PCE) is formulated as a mathematical programming problem and solved by optimizing the design factors including antenna geometry, operational frequencies, rectifier topologies, and rectifier parameters. An array of broadband high gain patch antennas with reconfigurable rectifiers, an impedance matching network, and a voltage-multiplier circuit are employed in the system to maximize the PCE. The voltage standing wave ratio (VSWR) and reflection coefficient (S11) of the antenna are estimated and optimized by numerical method. Simulations are conducted to evaluate the performances of the rectenna and the voltage-multiplier circuit. Results for radiation pattern, wave absorption, input impedance, voltage, and power across the load resistance as a function of frequency are obtained for the optimized configuration. The overall efficiency of the optimized RFEH system is measured at various power inputs and load resistances.

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Research of 0.2 THz broadband unbalanced multiplier circuit

Infrared and Laser Engineering ◽

10.3788/irla201746.0106003 ◽

2017 ◽

Vol 46 (1) ◽

pp. 106003 ◽

Cited By ~ 1

Author(s):

王俊龙 Wang Junlong ◽

杨大宝 Yang Dabao ◽

邢东 Xing Dong ◽

梁士雄 Liang Shixiong ◽

张立森 Zhang Lisen ◽

...

Keyword(s):

Multiplier Circuit

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Reversible Fault‐Tolerant Multiplier Circuit

Reversible and DNA Computing ◽

10.1002/9781119679455.ch15 ◽

2020 ◽

pp. 187-192

Keyword(s):

Fault Tolerant ◽

Multiplier Circuit

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Analysis and comparison of fast multiplier circuits based on different parameters

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.12945 ◽

2018 ◽

Vol 7 (3) ◽

pp. 1189

Author(s):

Mr Aaron D’costa ◽

Dr Abdul Razak ◽

Dr Shazia Hasan

Keyword(s):

Power Consumption ◽

High Speed ◽

Electronic Circuit ◽

Vlsi Circuit ◽

Silicon Area ◽

Lower Power ◽

Digital Electronics ◽

Design Specifications ◽

Important Design ◽

Multiplier Circuit

Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.

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