A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

2014 ◽  
Vol 61 (11) ◽  
pp. 3278-3287 ◽  
Author(s):  
Fan-Ta Chen ◽  
Min-Sheng Kao ◽  
Yu-Hao Hsu ◽  
Jen-Ming Wu ◽  
Ching-Te Chiu ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Phase Frequency Detector ◽  
Single Loop ◽  
Low Jitter ◽  
Frequency Detector ◽  
Rotational Phase

scholarly journals Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector

2020 ◽  
Vol 9 (5) ◽  
pp. 951-955
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Clock Recovery ◽  
Clock Frequency ◽  
Phase Frequency Detector ◽  
Delay Locked Loop ◽  
Design And Implementation ◽  
Frequency Detector

This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.

scholarly journals 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

2006 ◽  
Vol 4 ◽  
pp. 287-291
Author(s):  
S. Tontisirin ◽  
R. Tielert
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Data Recovery ◽  
Voltage Controlled Oscillator ◽  
Clock Generator ◽  
Low Jitter ◽  
Phase Clock ◽  
Multi Phase ◽  
Frequency Detector

Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.

Low-jitter design method based on n-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

2009 ◽  
Vol 45 (16) ◽  
pp. 808 ◽  
Author(s):  
K. Kishine ◽  
H. Inaba ◽  
Ma. Nakamura ◽  
Mi. Nakamura ◽  
Y. Ohtomo ◽  
...  
Keyword(s):  
Design Method ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Low Jitter
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