scholarly journals Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector

2020 ◽  
Vol 9 (5) ◽  
pp. 951-955
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Clock Recovery ◽  
Clock Frequency ◽  
Phase Frequency Detector ◽  
Delay Locked Loop ◽  
Design And Implementation ◽  
Frequency Detector

This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

scholarly journals DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER

2014 ◽  
pp. 82-86
Author(s):  
Shobhanjana Kalita ◽  
S. BABU ◽  
P.P. SAHU
Keyword(s):  
High Speed ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
High Data Rate ◽  
Center Frequency ◽  
High Q ◽  
High Data ◽  
Delay Locked Loop ◽  
Design And Implementation ◽  
Sc Filter

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.

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