Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays

2018 ◽  
Vol 65 (12) ◽  
pp. 1879-1883 ◽  
Author(s):  
A. D. Grasso ◽  
G. Palumbo ◽  
S. Pennisi
2011 ◽  
Vol 20 (07) ◽  
pp. 1277-1286 ◽  
Author(s):  
MERIH YILDIZ ◽  
SHAHRAM MINAEI ◽  
EMRE ARSLAN

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.


2009 ◽  
Vol 45 (24) ◽  
pp. 1199 ◽  
Author(s):  
C.-H. Tsai ◽  
J.-H. Wang ◽  
C.-T. Chang ◽  
C.-Y. Wang

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2309
Author(s):  
Hyoung-Rae Kim ◽  
Chang-Ho An ◽  
Bai-Sun Kong

A high-speed column driver IC with an area-efficient high-slew-rate buffer amplifier is proposed for use in a large-sized, high-resolution TFT-LCD panel application. In the proposed architecture, explicit isolation switches have been embedded into the buffer amplifier resulting in a fast settling response. The amplifier also has a structure that adjusts the tail current of the input stage using a very compact adaptive biasing. The proposed column driver IC, having the proposed buffer amplifier for driving a 55-inch 4K ultra-high-definition (UHD) TV panel, was fabricated in a 0.18-μm 1.8-V low-voltage, 1.2-μm 9-V medium-voltage, and 1.6-μm 18-V high-voltage CMOS process. The performance evaluation results indicated that 90% and 99.9% falling settling times were improved from 1.947 µs to 0.710 µs (63.5% improvement) and 4.131 µs to 2.406 µs (41.7% improvement), respectively. They also indicated that the layout size of the proposed buffer amplifier was reduced from 5580 μm2 to 4402 μm2 (21.1% reduction).


2011 ◽  
Vol 20 (07) ◽  
pp. 1377-1387 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO

A high-speed low-power rail-to-rail buffer amplifier, which is suitable for liquid crystal display driver applications, is proposed. An offset voltage is intentionally built in the second stage to cut off the transistors of last stage from the output node in the stable state and hence achieve low dc power consumption. The input referred offset voltage due to the built-in offset is very small. The buffer draws little current while static but has a large driving capability while transient. An experimental prototype buffer amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 30 × 98 μm2. The measured data show that the proposed output buffer amplifier is very suitable for LCD driver applications.


2015 ◽  
Vol 35 (3) ◽  
pp. 771-790 ◽  
Author(s):  
Sahar Sarafi ◽  
Abu Khari Bin Aain ◽  
Javad Abbaszadeh

Sign in / Sign up

Export Citation Format

Share Document