UV Illumination Technique for Leakage Current Reduction in a-Si:H Thin-Film Transistors

This study examines the effect of the annealing temperature on the initial electrical characteristics and photo-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). The extracted electrical parameters from transfer curves suggest that a low-temperature treatment maintains a high density of defects in the IGZO bulk, whereas high-temperature annealing causes a quality degradation of the adjacent interfaces. Light of short wavelengths below 460 nm induces defect generation in the forward measurement and the leakage current increases in the reverse measurement, especially for the low-temperature-annealed device. The hysteresis after negative-bias-illumination-stress (NBIS) is quantitatively investigated by using the double-scan mode and a positive gate pulse. Despite the abnormal transfer properties in the low-temperature-treated device, the excited holes are identically trapped at the front interface irrespective of treatment temperature. NBIS-induced critical instability occurs in the high-temperature-annealed TFT.

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The effect of electrical stress on the leakage current of polycrystalline Si thin-film transistors fabricated by metal-induced lateral crystallization

Thin Solid Films ◽

10.1016/j.tsf.2004.02.037 ◽

2004 ◽

Vol 466 (1-2) ◽

pp. 303-306 ◽

Cited By ~ 4

Author(s):

Yeo-Geon Yoon ◽

Gi-Bum Kim ◽

Tae-Kyung Kim ◽

Byung-Il Lee ◽

Seung-Ki Joo

Keyword(s):

Thin Film ◽

Leakage Current ◽

Thin Film Transistors ◽

Electrical Stress ◽

Lateral Crystallization ◽

Si Thin Film

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Extensive Leakage Current Reduction in Polymer Dielectric Thin Film by Metal Nanoparticles Incorporation for OTFT

10.7567/ssdm.2008.p-10-9 ◽

2008 ◽

Author(s):

T. H. Huang ◽

Z. Pei ◽

H. T. Lin ◽

S. W. Tsai ◽

Y. J. Chan

Keyword(s):

Thin Film ◽

Metal Nanoparticles ◽

Leakage Current ◽

Dielectric Thin Film ◽

Polymer Dielectric ◽

Current Reduction

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Hydrogen in Ultralow Temperature SiO2for Nanocrystalline Silicon Thin Film Transistors

MRS Proceedings ◽

10.1557/proc-814-i10.14 ◽

2004 ◽

Vol 814 ◽

Cited By ~ 1

Author(s):

Alex Kattamis ◽

I-Chun Cheng ◽

Steve Allen ◽

Sigurd Wagner

Keyword(s):

Thin Film ◽

Leakage Current ◽

Current Density ◽

Thin Film Transistors ◽

Secondary Ion Mass Spectrometry ◽

Crystalline Silicon ◽

Chemical Vapor ◽

Nanocrystalline Silicon ◽

Film Deposition ◽

Silicon Thin Film

AbstractNanocrystalline silicon is a candidate material for fabricating thin film transistors with high carrier mobilities on plastic substrates. A major issue in the processing of nanocrystalline silicon thin film transistors (nc-Si:H TFTs) at ultralow temperatures is the quality of the SiO2gate dielectric. SiO2deposited at less than 250°C by radio frequency plasma enhanced chemical vapor deposition (rf-PECVD), and not annealed at high temperature after deposition, exhibits high leakage current and voltage shifts when incorporated into TFT's. Secondary ion mass spectrometry (SIMS) measurements show that the hydrogen concentration (NH) in PECVD oxide deposited at 150°C on crystalline silicon (x-Si) is ∼ 0.8 at. %. This is much higher than in thermal oxides on x-Si, which display concentrations of less than 0.003 at. %. The leakage current density for thermal oxides on x-Si at a bias of 10 V is ∼9×10−6A/cm2whereas for 200°C PECVD oxides on nc-Si:H the current is ∼1×10−4A/cm2. As the temperature of the SiO2deposition is reduced to 150°C the current density rises by up to two orders of magnitude more. The H which is suspected to cause the leakage current across the PECVD oxide originates from the nc-Si:H substrate and the SiH4source gas. We analyzed the 300-nm gate oxide in capacitor structures of Al / SiO2/n+nc-Si:H / Cr / glass, Al / SiO2/ n+nc-Si:H / x-Si, and Al / SiO2/ x-Si. Vacuum annealing the nc-Si:H prior to PECVD of the oxide drives H out of the nc-Si:H film and reduces the amount of H incorporated into the oxide that is deposited on top. SiO2film deposition from SiH4and N2O at high He dilution has a still greater effect on lowering NH. The leakage current at a 10 V bias dropped from ∼1×10−4A/cm2to about ∼2×10−6A/cm2using He dilution at 250°C, and the vacuum anneal of the nc-Si:H lowered it by an additional factor of two. Thus we observe that both the nc-Si:H anneal and the SiO2deposition at high He dilution lessen the gate leakage current.

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Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156414500232 ◽

2014 ◽

Vol 23 (03n04) ◽

pp. 1450023 ◽

Cited By ~ 1

Author(s):

Olivier Bonnaud ◽

Peng Zhang ◽

Emmanuel Jacques ◽

Regis Rogel

Keyword(s):

Thin Film ◽

Leakage Current ◽

Thin Film Transistors ◽

Field Effect ◽

Field Effect Transistors ◽

Substrate Surface ◽

Vertical Channel ◽

Electrical Behavior ◽

Research Activities ◽

P Type

In order to pursue the integration, the research activities were oriented during the last years towards channel conduction in a plan perpendicular to the substrate surface while in the traditional architectures the conduction is parallel to the surface, under the gate. In the integrated technologies, this approach led to the FinFET. But in this case, even though the conduction plan is perpendicular to the substrate surface, the direction of the drain currents remains parallel to the substrate. New electronics devices were designed with the channels vertically oriented. In the monolithic technologies, many drawbacks have stopped this trend. However, in the case of thin film technologies, the approach appeared more suitable. The channel conduction is thus vertically oriented. But a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier in-between and the decrease of the thickness of the channel active layer, led to electrical behavior much more suitable for applications. After an overview of the different approaches developed as well in monolithic technologies as in thin film technologies, this presentation will give details on the concept and on the fabrication process of quasi-vertical thin film transistors. The associated electrical results will be described, analyzed and commented.

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