A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors
2011 ◽
Vol 58
(11)
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pp. 3890-3897
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2003 ◽
Vol 150
(5)
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pp. G307
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2008 ◽
Vol 85
(8)
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pp. 1804-1806
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2009 ◽
Vol 27
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pp. 1261
2011 ◽
Vol 32
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pp. 076001
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2010 ◽
Vol 242
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pp. 012010
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