Low cost test architecture for mixed-signal integrated circuits

2014 ◽  
Author(s):  
Julio L. da Silva ◽  
Emerson Camargo ◽  
Douglas Foster ◽  
Sandro T. Coelho ◽  
Antonio G. de Oliveira ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Cost ◽  
Mixed Signal ◽  
Test Architecture

scholarly journals Design automation of ΔΣ switched capacitor modulators using spice and MATLAB

2014 ◽  
Vol 11 (1) ◽  
pp. 47-59
Author(s):  
Dejan Mirkovic ◽  
Predrag Petkovic
Keyword(s):  
Integrated Circuits ◽  
Design Automation ◽  
Low Cost ◽  
Signal Design ◽  
Time Saving ◽  
Mixed Signal ◽  
Working Environments ◽  
High Level ◽  
Technology Processes ◽  
Simulation Time

Concerning the fact that the design of contemporary integrated circuits (IC) is practically impossible without using sophisticated Electronic Design Automation (EDA) software, this paper gives some interesting thoughts and considerations about that issue. As technology processes advances on year basis consequently EDA industry is forced to follow this trend as well. This, on the other hand, requires IC designer to frequently and efficiently accommodate to new working environments. Authors of this paper suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks. The paper demonstrates the proposed EDA procedure on an example of second order ?? modulator design. It illustrates considerable simulation time saving which is more than welcome in a world of analogue and mixed-signal design.

A Flexible, Low Cost Test System for Failure Analysis of High Power Mixed Signal ASICs

2003 ◽  
Author(s):  
T. Kolasa ◽  
J. C. De La Torre ◽  
L. Bertram
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
High Power ◽  
Low Cost ◽  
Test System ◽  
Modular Construction ◽  
Mixed Signal ◽  
Charge Pumps ◽  
Switching Power ◽  
Compact Size

Abstract In this paper, we will present our solution to the problem of test based fault localization in the failure analysis laboratory environment. The test system described herein is currently used for a number of high power mixed signal application specific integrated circuits (ASICs) that incorporate functions including switching power supplies, charge pumps, high current drivers, precision references, ADCs/DACs, comparator circuits, and digital cores. The solution addresses the shortcomings of alternative options through modular construction, compact size, and use of a commercially available graphical software compiler to create the control code and graphical user interface (GUI).

scholarly journals In-Plane Monolithic Integration of Scaled III-V Photonic Devices

2021 ◽  
Vol 11 (4) ◽  
pp. 1887
Author(s):  
Markus Scherrer ◽  
Noelia Vico Triviño ◽  
Svenja Mauthe ◽  
Preksha Tiwari ◽  
Heinz Schmid ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Photonic Devices ◽  
Monolithic Integration ◽  
Light Emitters ◽  
Fully Integrated ◽  
Large Lattice ◽  
Hybrid Iii ◽  
Gain Material

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

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