Fast circuit topology based method to configure the scan chains in Illinois Scan architecture

Author(s):  
Swapneel Donglikar ◽  
Mainak Banga ◽  
Maheshwar Chandrasekar ◽  
Michael S. Hsiao
Author(s):  
Ch.W. Lerche ◽  
V. Herrero-Bosch ◽  
M. Spaggiari ◽  
F. Mateo-Jimenez ◽  
J.M. Monz-Ferrer ◽  
...  

Author(s):  
Yu Huang ◽  
Wu-Tung Cheng ◽  
Ting-Pu Tai ◽  
Liyang Lai ◽  
Ruifeng Guo ◽  
...  

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.


2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Jiun-Wei Horng ◽  
Zih-Yang Jhao

A voltage-mode universal biquadratic filter using a differential voltage current conveyor (DVCC), two capacitors, and two resistors is presented. The proposed circuit has four input terminals and three output terminals and can realize all the standard filter functions, which are lowpass, bandpass, highpass, notch, and allpass filters, without changing the circuit topology. Three simultaneous output filter responses can be obtained from some derived filter types. The proposed circuit employs only one DVCC that simplifies the configuration.


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