Failure Analysis on Power Trench MOSFET Devices with Copper Wire Bonds

With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.

Non-Visible Defect Analysis of OTP Device

Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

Whisker Formation in Copper Electroplating

In the manufacture of Printed Wiring Boards (PWB), unwelcome structures, such as nodules and whiskers can be formed during copper electroplating with copper sulfate. Copper (Cu) whiskers with lengths of up to a few hundred micrometers can lead to electrical shorts between layers or patterns. In this paper, we document factors that can affect the growth of Cu whiskers; decomposition of additives in the Cu electroplating solution, surface stress, acidic cleaner, and the ingredients of a dry film. Contaminants from outside of the electroplating bath and the ingredients of the dry film were shown as key components in the formation of Cu whiskers.

Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis

This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.

Improving Wire Sweep Performance by Measuring Degree of Cure of Epoxy Mold Compounds

The choice of epoxy mold compound (EMC) for an electronic package is based mostly on how much protection it provides to the active components in the package. But the choice is not a straightforward process. Rather it is mostly trial and error using different assembly parameters to find the most robust material while assembly defects are monitored. One such defect associated to EMC processing is wire sweep, and many studies have shown that it is mainly caused by viscosity changes in the EMC. In this study, samples of EMC in various stages of shelf life and staging times were analyzed for degree of cure using a method called differential scanning calorimetry (DSC). Samples are then processed at assembly for wire sweep measurement. It was found out that degree of cure increases with staging time at different rates for each shelf life. It was also found out that wire sweep did not only increase with degree of cure but it was also found to be predictable with respect to the latter. Using this information, the age and staging limit for each material was identified that would not cause wire sweep issues.

Correcting for Spherical Aberrations in Solid Immersion Microscopy Using a Deformable Mirror

We present a method for correcting spherical aberrations in solid immersion microscopy through the use of a deformable mirror. Aberrations in solid immersion imaging for failure analysis can be induced through off-axis imaging, errors in lens fabrication or mismatch of design and substrate wafer thickness. RMS wavefront error correction of 30% is demonstrated in the case of substrate wafer thickness error.

Local Lattice Strain Measurement Using Geometric Phase Analysis of Dark Field Images from Scanning Transmission Electron Microscopy

Since strain engineering plays a key role in semiconductor technology development, a reliable and reproducible technique to measure local strain in devices is necessary for process development and failure analysis. In this paper, geometric phase analysis of high angle annular dark field - scanning transmission electron microscope images is presented as an effective technique to measure local strains in the current node of Si based transistors.

Thermal Frequency Imaging: A New Application of Laser Voltage Imaging Applied on 40nm Technology

For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

Electrical Failure and Damage Analysis of Multi-Layer Metal Films on Flexible Substrate during Cyclic Bending Deformation

The electrical resistance Cu film on flexible substrate was investigated in cyclic bending deformation. The electrical resistance of 1 µm thick Cu film on flexible substrate increased up to 120 % after 500,000 cycles in 1.1 % tensile bending strain. Crack and extrusion were observed due to the fatigue damage of metal film. Low bending strain did not cause any damage on metal film but higher bending strain resulted in severe electrical and mechanical damage. Thinner film showed higher fatigue resistance because of the better mechanical property of thin film. Cu film with NiCr under-layer showed poorer fatigue resistance in tensile bending mode. Ni capping layer did not improve the fatigue resistance of Cu film, but Al capping layer suppressed crack formation and lowered electrical resistance change. The NiCr under layer, Ni capping layer, and Al capping layer effect on electrical resistance change of Cu film was compared with Cu only sample.