Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

2011 ◽  
Author(s):  
Yu Huang ◽  
Wu-Tung Cheng ◽  
Ting-Pu Tai ◽  
Liyang Lai ◽  
Ruifeng Guo ◽  
...  
Keyword(s):  
Hold Time ◽  
Clock Signal ◽  
Clock Tree ◽  
Scan Testing ◽  
Design Error ◽  
Functional Logic ◽  
Scan Chains ◽  
Delay Defects

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing

2013 ◽  
Vol 30 (4) ◽  
pp. 60-70 ◽  
Author(s):  
Yuta Yamato ◽  
Kohei Miyase ◽  
Seiji Kajihara ◽  
Xiaoqing Wen ◽  
Laung-Terng Wang ◽  
...  
Keyword(s):  
Clock Tree ◽  
Scan Testing

Robust paradigm for diagnosing hold-time faults in scan chains

2007 ◽  
Vol 1 (6) ◽  
pp. 706 ◽  
Author(s):  
C.-W. Tzeng ◽  
J.-J. Hsu ◽  
S.-Y. Huang
Keyword(s):  
Hold Time ◽  
Scan Chains

scholarly journals Power and Obstacle Aware 3D Clock Tree Synthesis

2017 ◽  
Author(s):  
Leena Chandrakar ◽  
Ravi S. ◽  
Harish M. Kittur
Keyword(s):  
Integrated Circuits ◽  
Electrical Signal ◽  
Experimental Result ◽  
Clock Signal ◽  
Clock Tree ◽  
3D Ics ◽  
Clock Tree Synthesis ◽  
Flow Through ◽  
Vertical Interconnection ◽  
Tree Synthesis

Clock Network Design (CDN) is a critical step while designing any Integrated-Circuits (ICs). It holds vital importance in the performance of entire circuit. Due to continuous scaling, 3D ICs stacked with TSV are gaining importance, with an objective to continue with the Moore's law. Through-Silicon-Via (TSV) provides the vertical interconnection between two die, which allows the electrical signal to flow through it. 3D ICs has many advantages over conventional 2D planar ICs like reduced power, area, cost, wire-length etc. The proposed work is mainly focused on power reduction and obstacle avoidance for 3D ICs. Various techniques have already been introduced for minimizing clock power within specified clock constraints of the 3D CND network. Proposed 3D Clock Tree Synthesis (CTS) is a combination of various algorithms with an objective to meet reduction in power as well as avoidance of obstacle or blockages while routing the clock signal from one sink to other sink. These blockages like RAM, ROM, PLL etc. are fixed during the placement process. The work is carried out mainly in three steps- first is Generation of 3D Clock tree avoiding the blockages, then Buffering and Embedding and finally validating the results by SPICE simulation. The experimental result shows that our CTS approach results in significant 9% reduction in power as compare to the existing work.

A SAT-Based Methodology for Effective Clock Gating for Power Minimization

2018 ◽  
Vol 28 (01) ◽  
pp. 1950011
Author(s):  
Khushbu Chandrakar ◽  
Suchismita Roy
Keyword(s):  
Power Consumption ◽  
Optimization Techniques ◽  
Total Power ◽  
Clock Signal ◽  
Clock Gating ◽  
Clock Tree ◽  
Synchronous Circuits ◽  
Design And Optimization ◽  
Total Power Consumption ◽  
On Chip

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to raise the level of abstraction for the design and optimization. A better optimization of performance and power can be achieved at higher abstraction levels by applying suitable optimization techniques. Insertion of clock gating logic into the generated Register-Transfer Level (RTL) would facilitate lowering dynamic power consumption by switching off the clock signal to portions of the circuit not currently in use and thereby reducing unnecessary toggling. In this work, we have tried to minimize the power consumption of synchronous circuits by reducing the number of activity string patterns. Activity-driven clock trees have been used wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies additional control signals and gates, there is always a trade-off existing between the logic circuit area overhead and the total power consumption of the clock tree. A pseudo-Boolean satisfiability (PB-SAT)-based approach is proposed in this work which focuses on the reduction of power consumption by reducing the activity pattern of the clock tree which will reduce the power consumption with appropriate module-binding solutions.

On Debugging Intermittent Chain Hold-time Failures Caused by Process Variations for FinFET Technology

2020 ◽  
Author(s):  
Huaxing Tang ◽  
Allen Yang ◽  
Zhanjun Shu ◽  
Eden Cai ◽  
Shizhong Chen ◽  
...  
Keyword(s):  
Standard Method ◽  
Hold Time ◽  
Process Variations ◽  
Manufacturing Defects ◽  
Test Compression ◽  
Yield Learning ◽  
Scan Chains

Abstract Scan-based test has been the industrial standard method for screening manufacturing defects. Scan chains are vulnerable to most manufacturing defects and process variations. Therefore, chain failures diagnosis is critical for successful yield learning. However, traditional chain diagnosis requires failing masking patterns to identify faulty chains and their fault types for designs with test compression. In other words, it cannot diagnose the chain failures which don't fail the masking chain patterns. Unfortunately, advanced FinFET technologies with more manufacturing challenges and higher process variations may result in more subtle chain timing failures which can't be detected by chain masking patterns. In this work, we present a new debugging methodology, which combines chain diagnosis and tester-based test to effectively diagnose such intermittent chain failures. The proposed methodology is validated on silicon data for one modern large SOC design and successfully identified all scan cells with hold-time issues, which were validated by STA with corrected models. The subsequent mask fixes for these identified hold-time violations resolved this yield issue and dramatically improve the yield.

Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains

2005 ◽  
Vol 54 (11) ◽  
pp. 1467-1472 ◽  
Author(s):  
J.C.-M. Li
Keyword(s):  
Hold Time ◽  
Setup Time ◽  
Scan Chains

scholarly journals Automated Synthesis of Skew-Based Clock Distribution Networks

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 31-57 ◽  
Author(s):  
José Luis Neves ◽  
Eby G. Friedman
Keyword(s):  
Distribution Network ◽  
Distribution Networks ◽  
Clock Signal ◽  
Clock Distribution ◽  
Delay Model ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Distribution Networks ◽  
Clock Distribution Network ◽  
Interconnect Lines

In this paper a top-down methodology is presented for synthesizing clock distribution networks based on application-dependent localized clock skew. The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance and reliability; 2) design of the topology of the clock tree based on the circuit hierarchy and minimum clock path delays; 3) design of circuit structures to implement the delay values associated with the branches of the clock tree; and 4) design of the geometric layout of the clock distribution network. Algorithms to determine an optimal clock skew schedule, the optimal clock delay to each register, the network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS technology and a design strategy based on this technology is presented to implement the individual branch delays. The minimum number of inverters required to implement the branch delays is determined, while preserving the polarity of the clock signal. The clock lines are transformed from distributed resistive-capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. The inverters are specified by the geometric size of the transistors, the slope of the ramp shaped input/output waveform, and the output load capacitance. The branch delay model integrates an inverter delay model with an interconnect delay model. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock skew between any two registers belonging to the same global data path are obtained as compared with SPICE Level-3.

Skin Cooling on Breath-Hold Duration and Predicted Emergency Air Supply Duration During Immersion

2020 ◽  
Vol 91 (7) ◽  
pp. 578-585
Author(s):  
Victory C. Madu ◽  
Heather Carnahan ◽  
Robert Brown ◽  
Kerri-Ann Ennis ◽  
Kaitlyn S. Tymko ◽  
...  
Keyword(s):  
Minute Ventilation ◽  
Hold Time ◽  
Whole Body ◽  
Breath Hold ◽  
Endurance Time ◽  
Skin Exposure ◽  
Breathing Apparatus ◽  
Air Supply ◽  
Skin Cooling ◽  
Breath Hold Duration

PURPOSE: This study was intended to determine the effect of skin cooling on breath-hold duration and predicted emergency air supply duration during immersion.METHODS: While wearing a helicopter transport suit with a dive mask, 12 subjects (29 ± 10 yr, 78 ± 14 kg, 177 ± 7 cm, 2 women) were studied in 8 and 20°C water. Subjects performed a maximum breath-hold, then breathed for 90 s (through a mouthpiece connected to room air) in five skin-exposure conditions. The first trial was out of water for Control (suit zipped, hood on, mask off). Four submersion conditions included exposure of the: Partial Face (hood and mask on); Face (hood on, mask off); Head (hood and mask off); and Whole Body (suit unzipped, hood and mask off).RESULTS: Decreasing temperature and increasing skin exposure reduced breath-hold time (to as low as 10 ± 4 s), generally increased minute ventilation (up to 40 ± 15 L · min−1), and decreased predicted endurance time (PET) of a 55-L helicopter underwater emergency breathing apparatus. In 8°C water, PET decreased from 2 min 39 s (Partial Face) to 1 min 11 s (Whole Body).CONCLUSION: The most significant factor increasing breath-hold and predicted survival time was zipping up the suit. Face masks and suit hoods increased thermal comfort. Therefore, wearing the suits zipped with hoods on and, if possible, donning the dive mask prior to crashing, may increase survivability. The results have important applications for the education and preparation of helicopter occupants. Thermal protective suits and dive masks should be provided.Madu VC, Carnahan H, Brown R, Ennis K-A, Tymko KS, Hurrie DMG, McDonald GK, Cornish SM, Giesbrecht GG. Skin cooling on breath-hold duration and predicted emergency air supply duration during immersion. Aerosp Med Hum Perform. 2020; 91(7):578–585.

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

2011 ◽  
Vol E94-C (3) ◽  
pp. 288-295 ◽  
Author(s):  
Kazuyoshi TAKAGI ◽  
Yuki ITO ◽  
Shota TAKESHIMA ◽  
Masamitsu TANAKA ◽  
Naofumi TAKAGI
Keyword(s):  
Clock Tree ◽  
Clock Tree Synthesis ◽  
Tree Synthesis
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