A CML Ring Oscillator-Based Supply-Insensitive PLL With On-Chip Calibrations

2015 ◽  
Vol 63 (1) ◽  
pp. 233-243 ◽  
Author(s):  
Xiaoyan Gui ◽  
Peng Gao ◽  
Zhiming Chen
Keyword(s):  
Author(s):  
Xiaoxiao Wang ◽  
Pengyuan Jiao ◽  
Mehdi Sadi ◽  
Donglin Su ◽  
LeRoy Winemberg ◽  
...  
Keyword(s):  
Ir Drop ◽  

Author(s):  
Paul Clapera ◽  
Soumya Ray ◽  
Xavier Jehl ◽  
Marc Sanquer ◽  
Alexandre Valentian ◽  
...  

Sensors ◽  
2010 ◽  
Vol 10 (11) ◽  
pp. 10095-10104 ◽  
Author(s):  
Ming-Zhi Yang ◽  
Ching-Liang Dai ◽  
De-Hao Lu

Sensors ◽  
2009 ◽  
Vol 9 (12) ◽  
pp. 10158-10170 ◽  
Author(s):  
Ching-Liang Dai ◽  
Po-Wei Lu ◽  
Chienliu Chang ◽  
Cheng-Yang Liu

Cryptography ◽  
2018 ◽  
Vol 2 (3) ◽  
pp. 15 ◽  
Author(s):  
Don Owen Jr. ◽  
Derek Heeger ◽  
Calvin Chan ◽  
Wenjie Che ◽  
Fareena Saqib ◽  
...  

Secure booting within a field-programmable gate array (FPGA) environment is traditionally implemented using hardwired embedded cryptographic primitives and non-volatile memory (NVM)-based keys, whereby an encrypted bitstream is decrypted as it is loaded from an external storage medium, e.g., Flash memory. A novel technique is proposed in this paper that self-authenticates an unencrypted FPGA configuration bitstream loaded into the FPGA during the start-up. The internal configuration access port (ICAP) interface is accessed to read out configuration information of the unencrypted bitstream, which is then used as input to a secure hash function SHA-3 to generate a digest. In contrast to conventional authentication, where the digest is computed and compared with a second pre-computed value, we use the digest as a challenge to a hardware-embedded delay physical unclonable function (PUF) called HELP. The delays of the paths sensitized by the challenges are used to generate a decryption key using the HELP algorithm. The decryption key is used in the second stage of the boot process to decrypt the operating system (OS) and applications. It follows that any type of malicious tampering with the unencrypted bitstream changes the challenges and the corresponding decryption key, resulting in key regeneration failure. A ring oscillator is used as a clock to make the process autonomous (and unstoppable), and a novel on-chip time-to-digital-converter is used to measure path delays, making the proposed boot process completely self-contained, i.e., implemented entirely within the re-configurable fabric and without utilizing any vendor-specific FPGA features.


Author(s):  
Young-Jae An ◽  
Dong-Hoon Jung ◽  
Kyungho Ryu ◽  
Hyuck Sang Yim ◽  
Seong-Ook Jung
Keyword(s):  

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3413 ◽  
Author(s):  
Augusto Ximenes ◽  
Preethi Padmanabhan ◽  
Edoardo Charbon

Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase/delay-locked loops (PLLs/DLLs). Other methods, such as relative timing measurement (start/stop), require constant foreground calibration, which is not feasible for outdoor applications, where conditions of temperature, background illumination, etc. can change drastically and frequently. In this paper, a scalable reference generation and synchronization is provided, using minimum resources of area and power, while being robust to mismatches. The suitability of this approach is demonstrated through the design of an 8 × 8 time-to-digital converter (TDC) array, distributed over 1.69 mm2, fabricated using TSMC 65 nm technology (1.2 V core voltage and 4 metal layers—3 thin + 1 thick). Each TDC is based on a ring oscillator (RO) coupled to a ripple counter, occupying a very small area of 550 μ m2, while consuming 500 μ W of power, and has 2 μ s range, 125 ps least significant bit (LSB), and 14-bit resolution. Phase and frequency locking among the ROs is achieved, while providing 18 dB phase noise improvement over an equivalent individual oscillator. The integrated root mean square (RMS) jitter is less than 9 ps, the instantaneous frequency variation is less than 0.11%, differential nonlinearity (DNL) is less than 2 LSB, and integral nonlinearity (INL) is less than 3 LSB.


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