nMOS Transistor Location Adjustment for N-Hit Single-Event Transient Mitigation in 65-nm CMOS Bulk Technology

2018 ◽  
Vol 65 (1) ◽  
pp. 418-425 ◽  
Author(s):  
Zhenyu Wu ◽  
Shuming Chen
Keyword(s):  
Single Event ◽  
Single Event Transient ◽  
Nmos Transistor ◽  
Location Adjustment ◽  
Bulk Technology

scholarly journals Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

2021 ◽  
Vol 2137 (1) ◽  
pp. 012031
Author(s):  
Bohan Zhang ◽  
Bin Liang ◽  
Yahao Fang
Keyword(s):  
Temperature Sensitivity ◽  
Pulse Width ◽  
Single Event ◽  
Single Event Transient ◽  
Worst Case ◽  
Deep Well ◽  
Influence Of Temperature On ◽  
Radiation Resistant ◽  
Bulk Technology ◽  
28 Nm

Abstract The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

Single Event Transient (SET) Mitigation Circuits with Immune Leaf Nodes

2021 ◽  
pp. 1-1
Author(s):  
Faisal Mustafa Sajjade ◽  
Neeraj Kumar Goyal ◽  
B.K.S.V.L Varaprasad
Keyword(s):  
Single Event ◽  
Single Event Transient
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