Study of single event transient induced by heavy‐ion in NMOS transistor and CMOS inverter

2018 ◽  
Vol 31 (12) ◽  
Author(s):  
Cheng Gao ◽  
Rui Zhang ◽  
Jiaoying Huang ◽  
Chengcheng Fu
Symmetry ◽  
2019 ◽  
Vol 11 (2) ◽  
pp. 154 ◽  
Author(s):  
Jizuo Zhang ◽  
Jianjun Chen ◽  
Pengcheng Huang ◽  
Shouping Li ◽  
Liang Fang

In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV·cm2/mg) and 23% (at LET = 22.2 MeV·cm2/mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.


2017 ◽  
Vol 60 (12) ◽  
Author(s):  
Jinxin Zhang ◽  
Hongxia Guo ◽  
Fengqi Zhang ◽  
Chaohui He ◽  
Pei Li ◽  
...  

2002 ◽  
Vol 49 (6) ◽  
pp. 3121-3128 ◽  
Author(s):  
S.D. LaLumondiere ◽  
R. Koga ◽  
P. Yu ◽  
M.C. Maher ◽  
S.C. Moss

2008 ◽  
Vol 55 (4) ◽  
pp. 2001-2006 ◽  
Author(s):  
D. Truyen ◽  
J. Boch ◽  
B. Sagnes ◽  
J.-R. Vaille ◽  
N. Renaud ◽  
...  

2020 ◽  
Vol 35 (10) ◽  
pp. 105010
Author(s):  
Guoliang Tian ◽  
Jinshun Bi ◽  
Gaobo Xu ◽  
Kai Xi ◽  
Xueqin Yang ◽  
...  

2014 ◽  
Vol 918 ◽  
pp. 237-242
Author(s):  
Bin Zhou ◽  
Xin Chun Wu ◽  
Ming Xue Huo

Single event transient of a PMOS using strained Silicon-Germanium in a sub-100nm bulk process is studied by 3D TCAD simulation. The impact of bias voltage, temperature, LET, and struck position on SET is considered. Our simulation results demonstrate that bias voltage in the range 0.8 to 1.2V greatly influence the amplitude of SET current. Temperature has a stronger influence on a SiGe channel PMOS than a Si-channel PMOS. Both SET current duration and total collection charge increase as LET increases, and SET current duration and total collection of a SiGe channel PMOS are larger than that of Si channel PMOS. These simulation results are beneficial to the space application of SiGe circuits.


2012 ◽  
Vol 48 (3) ◽  
pp. 171 ◽  
Author(s):  
K. Schweiger ◽  
M. Hofbauer ◽  
H. Dietrich ◽  
H. Zimmermann ◽  
K.O. Voss ◽  
...  

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