A Novel Layout-Based Single Event Transient Injection Approach to Evaluate the Soft Error Rate of Large Combinational Circuits in Complimentary Metal-Oxide-Semiconductor Bulk Technology

2016 ◽  
Vol 65 (1) ◽  
pp. 248-255 ◽  
Author(s):  
Yankang Du ◽  
Shuming Chen
Keyword(s):  
Metal Oxide ◽  
Error Rate ◽  
Metal Oxide Semiconductor ◽  
Soft Error ◽  
Oxide Semiconductor ◽  
Combinational Circuits ◽  
Single Event ◽  
Single Event Transient ◽  
Soft Error Rate ◽  
Bulk Technology

scholarly journals Single event transient propagation in dynamic complementary metal oxide semiconductor cascade circuits

2015 ◽  
Vol 12 (23) ◽  
pp. 20150849-20150849 ◽  
Author(s):  
Jingyan Xu ◽  
Shuming Chen ◽  
Pengcheng Huang ◽  
Peipei Hao ◽  
Ruiqiang Song ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Single Event ◽  
Single Event Transient

scholarly journals LIHL: Design of a Novel Loop Interlocked Hardened Latch

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2090
Author(s):  
Hui Xu ◽  
Xuan Liu ◽  
Guo Yu ◽  
Huaguo Liang ◽  
Zhengfeng Huang
Keyword(s):  
Power Dissipation ◽  
High Reliability ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Metal Oxide Semiconductor ◽  
Soft Error ◽  
Oxide Semiconductor ◽  
Low Power Consumption ◽  
Single Event ◽  
Single Event Transient

A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches.

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