This paper presents a statistically-driven two-step flash sub-analog-to-digital converter (ADC) to construct the high-speed time-interleaved ADC in wireline communication applications. The comparators in the flash sub-ADC are divided into the large probability first stage and the small probability second stage to take advantage of the nonuniform probability distribution of the input signal. At the first step of operation, the large probability first stage is activated while the small probability second stage is suspended. If the input signal is beyond the input range of the first stage, the segment selection signal will trigger proper segment in the second stage. Feed-forward equalization is proposed to manipulate the probability distribution of the ADC input signal. A possible implementation of the proposed ADC as well as the modulation and equalization scheme is presented to comply with the IEEE 802.3ap 10[Formula: see text]G Ethernet standard. In the case of a PAM-4 pseudorandom signal, the proposed solution achieves [Formula: see text] reduction on the average number of activated comparators compared to a conventional flash ADC.
Low-power 6-bit flash ADC for high-speed data converters architectures
