A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications

This paper presents a statistically-driven two-step flash sub-analog-to-digital converter (ADC) to construct the high-speed time-interleaved ADC in wireline communication applications. The comparators in the flash sub-ADC are divided into the large probability first stage and the small probability second stage to take advantage of the nonuniform probability distribution of the input signal. At the first step of operation, the large probability first stage is activated while the small probability second stage is suspended. If the input signal is beyond the input range of the first stage, the segment selection signal will trigger proper segment in the second stage. Feed-forward equalization is proposed to manipulate the probability distribution of the ADC input signal. A possible implementation of the proposed ADC as well as the modulation and equalization scheme is presented to comply with the IEEE 802.3ap 10[Formula: see text]G Ethernet standard. In the case of a PAM-4 pseudorandom signal, the proposed solution achieves [Formula: see text] reduction on the average number of activated comparators compared to a conventional flash ADC.

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An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.1049-1050.687 ◽

2014 ◽

Vol 1049-1050 ◽

pp. 687-690

Author(s):

Yu Han Gao ◽

Ru Zhang Li ◽

Dong Bing Fu ◽

Yong Lu Wang ◽

Zheng Ping Zhang

Keyword(s):

High Speed ◽

Binary Code ◽

Sampling Rate ◽

Gray Code ◽

Cmos Technology ◽

Careful Consideration ◽

Analog To Digital ◽

Interleaved Adc ◽

Time Interleaved ◽

Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

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NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER

Journal of Circuits System and Computers ◽

10.1142/s021812660400191x ◽

2004 ◽

Vol 13 (06) ◽

pp. 1183-1201

Author(s):

KAMAL EL-SANKARY ◽

ALI ASSI ◽

MOHAMAD SAWAN

Keyword(s):

High Speed ◽

Sampling Method ◽

Dynamic Range ◽

Sampling Rate ◽

Analog To Digital ◽

Wireless Transceiver ◽

Spurious Free Dynamic Range ◽

Interleaved Adc ◽

Time Interleaved ◽

Free Dynamic

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

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HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156405003211 ◽

2005 ◽

Vol 15 (02) ◽

pp. 297-317 ◽

Cited By ~ 5

Author(s):

AHMED GHARBIYA ◽

TREVOR C. CALDWELL ◽

D. A. JOHNS

Keyword(s):

Discrete Time ◽

Input Signal ◽

Continuous Time ◽

High Frequency ◽

High Speed ◽

State Of The Art ◽

Analog To Digital Converters ◽

Analog To Digital ◽

Time Interleaved

This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

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Time-Interleaved Analog-to-Digital converter used for high-speed communication

Network Security and Communication Engineering ◽

10.1201/b18660-137 ◽

2015 ◽

pp. 531-536

Keyword(s):

High Speed ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Time Interleaved

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A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-015-0624-x ◽

2015 ◽

Vol 85 (2) ◽

pp. 299-310 ◽

Cited By ~ 1

Author(s):

Hayun Chung ◽

Zeynep Toprak Deniz ◽

Alexander Rylyakov ◽

John Bulzacchelli ◽

Daniel Friedman ◽

...

Keyword(s):

Flash Adc ◽

Interleaved Adc ◽

Time Interleaved

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Time-Interleaved ADC Gain Mismatch Calibration in High-Speed OFDM Systems

10.1145/3475971.3475972 ◽

2021 ◽

Author(s):

Vo Trung Dung Huynh ◽

Mai Linh ◽

Minh N.T. Nguyen ◽

Hien Ta ◽

Duc Trung Nguyen

Keyword(s):

High Speed ◽

Ofdm Systems ◽

Interleaved Adc ◽

Time Interleaved

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Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2016.2636209 ◽

2017 ◽

Vol 64 (5) ◽

pp. 1019-1030 ◽

Cited By ~ 19

Author(s):

Benjamin T. Reyes ◽

Raul M. Sanchez ◽

Ariel L. Pola ◽

Mario R. Hueda

Keyword(s):

Experimental Evaluation ◽

Communication Systems ◽

High Speed ◽

Calibration Algorithm ◽

Interleaved Adc ◽

Time Interleaved

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A Statistic-Based Calibration Method for TIADC System

Mathematical Problems in Engineering ◽

10.1155/2015/689869 ◽

2015 ◽

Vol 2015 ◽

pp. 1-9 ◽

Cited By ~ 1

Author(s):

Kuojun Yang ◽

Shulin Tian ◽

Peng Ye ◽

Peng Zhang ◽

Yuanjin Zheng

Keyword(s):

Sampling Rate ◽

Calibration Method ◽

Wide Frequency Range ◽

Accurate Estimation ◽

Analog To Digital ◽

Average Value ◽

Gain Error ◽

Sampling Points ◽

Interleaved Adc ◽

Time Interleaved

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

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A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽

10.3390/electronics8030305 ◽

2019 ◽

Vol 8 (3) ◽

pp. 305 ◽

Cited By ~ 1

Author(s):

Dong Wang ◽

Xiaoge Zhu ◽

Xuan Guo ◽

Jian Luan ◽

Lei Zhou ◽

...

Keyword(s):

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Sar Adc ◽

Oxide Semiconductor ◽

Power Measurement ◽

Cmos Process ◽

Analog To Digital ◽

Full Speed ◽

Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

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